Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend?

By Ali Khakifirooz (Spansion)

One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward body bias (FBB) is available owing to oxide isolation and the use of flip-well structure [1].

While designers are familiar with the concept of body biasing and have been using it in different forms for many years in bulk CMOS technology, concerns are occasionally raised – often from non-designers – about the complexity and effectiveness of body biasing in advanced nodes.

Body biasing has been known for many years [2] and was in fact identified as a key technology enabler in sub-0.1µm era by industry leaders [3]. Although ironically the recent move to the FinFET structure removed this gadget from the designers’ toolbox, the need for body biasing is still echoed [4].

Early studies demonstrated the effectiveness of body biasing in reducing leakage, improving performance, and reducing variability and thereby worst-case power consumption in complex circuits [5-7]. It was, however, pointed out that due to the competing effect of other leakage mechanisms, such as band-to-band tunneling, the effectiveness of reverse body bias (RBB) in managing leakage diminishes with technology scaling [8]. Nonetheless Intel continued using body biasing at least down to 45nm node [9].


Static Body Biasing

Device variability is one of the key detractors of product yield. Historically, the desktop-driven semiconductor industry used product binning to turn this natural performance variability into profit. However, it is known that changes in market demand or process may lead to significant imbalance between the demand and inventory [10]. Moreover, with the emergence of mobile applications as the dominant technology driver [4] and strict power requirements, binning is not effective anymore. With the desire to reduce VDD below 0.8V in order to reduce active power, managing the device variability becomes increasingly important.

Body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.

For example, in a media processor design in 65nm technology a 20% reduction in the worst-case delay was achieved by using an embedded FBB circuit [11]. While most body biasing designs are geared toward keeping VT constant, it has been shown that a combination of VT and drive current control leads to significantly tighter distribution (an 85% reduction in variation) and 25% reduction in total power [12]. These numbers are well comparable to the power saving expected from scaling the design by one technology node. Given the concerns about the saturation of cost scaling beyond 28nm, an FD-SOI design with a wide range of body biasing is thus very appealing.


Dynamic Body Biasing

For applications with varied workload, a more elaborate use of body bias is to adjust the transistor performance based on the workload. This can be, of course, combined with other known low-power techniques such as dynamic voltage and frequency scaling (DVFS), sleep transistors, power gating, etc. In particular, when combined with DVFS, the optimum VT for each VDD can be used to minimize total power [1].


Design Complexity and Area Overhead

Potentially added design complexity and area overhead due to body bias generation circuits and routing is sometimes voiced as a concern. Static body biasing is relatively easy to implement. Depending on the level of sophistication it requires some sensing circuits (leakage, delay, skew, temperature, etc.), charge pump circuits to generate the body bias, and a network to distribute it across the chip. In typical designs, this does not impose more than 1-2% area overhead. The design complexity is actually reduced as less resources are needed to meet target performance across process and temperature corners. Notable bulk CMOS designs that used body bias to reduce variability include Samsung’s ExynosTM SoC in both 32nm and 28nm node [13-14], and Oracle’s SPARC processors in 40nm [15].

Dynamic body biasing, on the other hand, needs additional system and software development. However, we do not expect this to be more complex than implementing any other low-power technique such as dynamic voltage scaling. An example is TI’s 45nm OMAP SoC that used body bias as a part of their SmartReflex technology (Figure 1) [16].



Figure 1. Example of combined dynamic body bias and voltage scaling in TI’s 45nm SoC [16]. Proper VDD and body bias is selected based on the power mode and process corner. (Courtesy: ISSCC, TI)

No Body Effect?

While many bulk CMOS designs used body bias in some form, on the other end of the spectrum are the designs that used PD-SOI technology, where majority of the devices do not have a body contact. The lack of body effect in PD-SOI devices was claimed to help stacked transistors and passgates, leading to 15-25% speed improvement [17]. For designers that prefer a zero-body-effect style, the move to FinFET or a thick BOX FD-SOI structure seems more natural. However, for mainstream applications where power and parametric yield are the main drivers, thin BOX FD-SOI and use of body bias is more sensible.

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[1] D. Jacquet, et al., “A 3 GHz dual core processor ARM CortexTM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization,” IEEE JSSC, p. 812, 2014.

[2] M. Kube, R. Hori, O. Minato, and K. Sato, “A threshold voltage controlling circuit for short channel MOS integrated circuits,” ISSCC, p. 54, 1976.

[3] S. Thompson, I. Young, J. Greason, and M. Bohr, “Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 µm logic designs,” Symp. VLSI Tech., p. 69, 1997.

[4] G. Yeap, “Smart mobile SoCs driving the semiconductor industry: technology trend, challenges and opportunities,” IEDM Tech. Dig., p. 1.3.1, 2013.

[5] M. Miyazaki, et al., “A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias,” ISSCC, p. 420, 2000.

[6] S. Narendra, et al., “1.1V 1GHz communication router with on-chip body bias in 150nm CMOS,” ISSCC, p. 218, 2002.

[7] J. Tchanz, et al., “Adaptive body bias for reducing impact of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” ISSCC, p. 422, 2002.

[8] A. Keshavarzi, et al., “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s,” ISLPED, p. 252, 1999.

[9] F. Hamzaoglu, et al., A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal-gate CMOS technology,” ISSCC, p. 376, 2008.

[10] J.Y. Chen, “GPU technology trends and future requirements,” IEDM Tech. Dig., p. 3, 2009.

[11] S. Nomura, et al., “A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology,” ISSCC, p. 262, 2008.

[12] M. Sumita, et al., “Mixed body-bias technique with fixed Vt and Ids generation circuits,” ISSCC, p. 158, 2004.

[13] S.-H. Yang, et al., “A 32nm high-k metal gate application processor with GHz multi-core CPU,” ISSCC, p. 214, 2012.

[14] Y. Shin, et al., “28nm high-k metal-gate heterogeneous quad-core CPUs for high-performance and energy efficient mobile application processor,” ISSCC, p. 154, 2013.

[15] J.L. Shin, et al., “A 40nm 16-core 128-thread CMT SPARC SoC processor,” ISSCC, p. 98, 2010.

[16] G. Gammie, et al., “A 45nm 3.5G baseband-and-multimedia application processor sing adaptive body-bias and ultra-low-power techniques, ISSCC, p. 258, 2008.

[17] M. Canada, et al., “A 580MHz RISC microprocessor in SOI,” ISSCC, p. 430, 1999.

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