2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May


IEEE_EDS_header

IEEE International

SOI-3D-Subthreshold Microelectronics Technology Unified Conference

6-9 October 2014

Westin San Francisco Airport, Millbrae, CA

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).

 

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Photo Credit: Catherine Allibert

Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.

The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

The 2014 edition of the conference already promises a rich content of high-level presentations.

 

 

Program

The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.

Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.

On the same webpage, more information is given about the various dedicated sessions.

There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.

 

Scope of the conference

The Committee will review papers submitted by May 26 in the three following focus areas of the conference:

  • Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.
  • Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.
  • 3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.

 

LocationIMG_0937-Revue

The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.

Important dates:

Paper submission deadline: 26 May 2014

Notification of acceptance: 23 June 2014

Short course date: 6 October 2014

Conference date: 6 – 9 October 2014

More details are available on the S3S website.

IMG_1037_revu2
Photo Credit: Catherine Allibert
 

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