A debate is raging over at SemiWiki following a post there entitled “Is SOI Really Less Expensive?” by Scotten Jones (you can read it here). Within just over 48 hours, about 30 comments were made, with heavy hitters on both sides of the fence weighing in.
While the post itself is about manufacturing economics, the comments delve deep into process minutiae. Many are extremely technical, written by people who are actually designing in FD-SOI, or who were part of the team that developed the technology.
Jones has a company called IC Knowledge, which, he notes, “…produces the most widely used IC cost modeling software in the semiconductor industry.” While seeing a slight cost advantage for 28n FD-SOI, he concluded that “…costs for planar FDSOI and FinFETs on bulk or SOI are all comparable at the 14nm node. Decisions on which process to pursue are therefore expected to be driven by factors other than cost.”
However, the FD-SOI ecosystem has found that FD-SOI provides much more substantial cost savings than the competing technologies. As always, the devil’s in the details, and commenters left no stone unturned.
If you read Jones’ post, make sure you save time to get through all the comments. If you don’t have time, at least page over to the excellent comment posted by Eric Esteve of IPNest (it’s on the bottom of the second page of coments – or you’ll find it here). He argues very persuasively that FD-SOI should and does come in substantially cheaper – 10% cheaper, in fact – for two major reasons: starting wafer cost and mask layer savings.
Esteve suggests that Jones’ starting wafer cost for FD-SOI does not allow for any decrease in cost that would typically be expected with high volumes. That makes a significant difference right there.
He then goes on to say that Jones’ estimation of mask layers does not take into account the favorable impact of multiple threshold voltages (Vt) inherent in FD-SOI. This gets fairly technical, so here’s his explanation in its entirety:
Inserting the same number of Vt (3) in the table for Bulk and FD-SOI is not accurate: FD-SOI offer consists of only 2Vts and wide leakage control/optimization is reached through the use of multichannel libraries allowing to accommodate from 24nm to 40nm channel length in the std-cells pitch. For the same leakage control, with bulk technology you would have to use 4 Vts. The same applies on bitcells where to get the same range of the FD-SOI offer, bulk technologies have to differentiate several specific implants, adding masks.
Why using multiple Vt approach? FD-SOI technology allows in the std-cells pitch to accommodate multi-channel libraries with the Lpoly ranging from Lmin=24nm to 40nm. This gives a great control over leakage when optimizing for power an implementation. The 2 Vts offered by FD-SOI provide a control over leakage of 1/200x (RVT L=40nm being 1/200 of the leakage of LVT Lmin=24nm, the leakiest device). To get the same leakage control range in a bulk technology (that allows a much reduced multichannel range), you need to use 4 Vts in a SoC.
FD-SOI library requires only using two Vt when using an equivalent library (optimizing the leakage current) on Bulk will require at least four Vt. The bottom line is that we [note: here he’s talking about Jones’ analysis] count more masks on FDSOI than needed (to be removed) and less masks on Bulk (to be added), the difference being 4 to 5 masks levels, or another (-5%)!
That is, you pass from par (100% normalized price for each technology in 28 nm) to 100% for Bulk to be compared with 90% for FD-SOI 28nm. The industry consensus is that 28nm will stay for long, and is the preferred node for cost sensitive products (like low-end wireless application processor), thus a 10% cost difference is really important.
The same argumentation applies for 14 nm technologies. Even if the decision to select FinFET is not purely based on cost, but on better performance or leakage behavior, a 10% cost difference may have a certain impact, when making the decision. Moreover, if we consider on the edge devices processed in 14nm, the unit price is expected to be high.
If you remember, we have mentioned the Forward Body Bias (FBB) capability available with FD-SOI. FBB allows either decreasing power, either increasing performance (frequency) of the same chip. But in a wafer fab, the same device is not processed the same way: it can be Slow, Typical of Fast, and you know it after test. When dealing with high variability, you may end up losing some yield because of it. FD-SOI has FBB as a plus for playing with process compensation, to eventually recover slow parts.
If your application requires chips in the high range or performance, that means that you have to trash a part of the production… except if you use FBB to compensate. Thus, you can keep the chip price in the acceptable range, as you can increase the number of good die (in respect with the performance) per wafer… This cost impact is difficult to quantify, as it will depend on the unit price, the level of performance, but we know from Intel marketing for processors that it can be high.
To summarize, even if a few percent cost difference may look negligible, the aggregation of these “small” differences lead to a 10% difference on the processed wafer cost. 28 nm technology node is expected to stay the mainstream for very long, due to the Moore’s law interruption, especially for the high volume, cost sensitive devices like low-cost application processor. As far as I remember from my ASIC PMM days, a 10% difference in unit cost is all but negligible when you negotiate with a customer, thus I suggest using the right wafer price from the beginning.
The devices implemented in 14 nm are probably not cost sensitive, but rather chase for high performance and/or ultra-low power. But is it a reason for pricing FD-SOI 10% higher than it should be?