Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).
This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported. Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.
Low Power Conference
It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go. He indicates a major announcement is impending.
Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!
ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality. He sees it having a very long life, with monolithic 3D stacking replacing scaling.
The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.
Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers. His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.
Shiro Kamohara, Chief Engineer of the Low Power Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT. They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.
A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share. For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.
A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said. He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.
Power (high & smart), power (very low), 3D and more
During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”. While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.
There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%. Look for more breakthroughs in their paper at IEDM this December, she said.
And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)
So it was a great show – kudos to the folks at Semi. Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.