10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

iedm_logoFD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we have a rundown of the top SOI-based advanced CMOS papers. In Part 2, we’ll cover papers on future device architectures. In Part 3 we’ll look at the papers on MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

 

The FD-SOI Papers

9.1: FD-SOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node.

Q. Liu et al (STMicroelectronics, CEA-LETI, IBM, Soitec)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)
In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In this work, researchers from STMicroelectronics and the IBM Technology Development Alliance demonstrate the successful implementation of strained FDSOI devices with LG, spacer & BOX dimensions scaled to 10nm feature sizes.

Two additional enabling elements for scaling FD-SOI devices to the 10nm node are reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 µA/µm for NFET at Ioff=1 nA/um (the highest performing FD-SOI NFET ever reported), and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 µA/µm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL are also reported.

 

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14. (Courtesy: ST et al, IEDM 2014)
[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14.
(Courtesy: ST et al, IEDM 2014)
7.2: A Mobility Enhancement Strategy for sub-14nm Power-efficient FDSOI Technologies

B. De Salvo et al. (Leti, ST, IMEP, IBM, Soitec)

This paper presents an original multi-level evaluation methodology for stress engineering device design of next-generation power-efficient devices. Ring oscillator simulations showed that a dynamic power gain of 50% could be achieved while maintaining circuit frequency performance thanks to the use of efficient mobility boosters. Thus a clear scaling path to achieve high-mobility, power-efficient sub-14nm FDSOI technologies has been identified.

 

3.4: Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-Voltage Range SRAM Operation in 28nm UTBB FD-SOI

O. Thomas et al (UC Berkeley, ST)

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than 100fA/bitcell are measured in a 140kb programmable dynamic SRAM. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

 

27.5: New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration

C. Fenouillet-Beranger et al (Leti, ST, LASSE)

For the first time the maximum thermal budget of in-situ doped source/drain state-of-the-art FD-SOI bottom MOSFET transistors is quantified to ensure transistors stability in Monolithic 3D (M3D) integration. Thanks to silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Thanks to in-depth morphological and electrical characterizations, it shows very promising results for high performance Monolithic 3D integration.

 

9.2 Future Challenges and opportunities for Heterogeneous process technology. Toward the thin films, Zero intrinsic Variabiliiy devices, Zero power Era (Invited)

S. Deleonibus et al (Leti)

By 2025, 25 % of the World Gross Domestic Product will depend on the development of Information and Communication Technologies . Less greedy device, interconnect, computing technologies and architectures are essential to aim at x1000 less power consumption.

IBM’s SOI-FinFET, eDRAM and 3D Papers

32.1: Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme

H. Tsai et al (IBM)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)
These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision. In this paper, IBM researchers present the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node.

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)
(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

 

Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)
Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

 

3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News)

C-H. Lin et al (IBM)

The IBM team presents a fully integrated 14nm CMOS technology featuring FinFET architecture on an SOI substrate for a diverse set of SoC applications including high-performance server microprocessors and low-power ASICs. A unique dual workfunction process optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel and without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. Because the technology is envisioned for use in SoC applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom than ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

The SOI FinFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

 

16.1: First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications

P. Hashemi et al (IBM)

Strained SiGe FinFETs are a promising PMOS technology for the 10nm technology node and beyond, due to their excellent electrostatics and built-in uniaxial compression. Yet while SiGe FinFETs with moderate germanium (Ge) content have been characterized, little data exists on FinFETs with high Ge  content. And, what little data does exist is mostly focused on relaxed or strained pure Ge. For the first time anywhere, IBM detailed CMOS-compatible, low-power and high-performance SiGe PMOS FinFETs with more than 50% Ge content. The devices feature ultra-narrow fin widths – down to 3.3 nm – which provide excellent short-channel control for low-power applications.  Using a Si-cap-free passivation process, they report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1e13 cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. They demonstrated the highest performance ever reported (Ion=0.42mA/µm and Ioff=100nA/µm) for sub-20nm PMOS FinFETs at 0.5 V.

 

19.4: 0.026µm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications

C. Pei et al (IBM)

This paper presents the industry’s smallest eDRAM based on IBM’s 22nm (partially depleted) SOI technology, which has been recently leveraged for IBM’s 12-core 649mm2 Server Processor POWER8™. It summarizes the n-band resistance innovations, and reports for the first time the asymmetric embedded stressor, cavity implant and through gate implant employed in 22nm eDRAM technology. The fully integrated 256Mb product array has demonstrated capability of 1.4ns cycle time, which is significantly faster than any other embedded DRAM.

 

14.6: Through Silicon Via (TSV) Effects on Devices in Close Proximity– the Role of Mobile Ion Penetration – Characterization and Mitigation

C. Kothandaraman et al (IBM)

The research team identified and studied a new interaction between TSV processes and devices in close proximity, different from mechanical stress. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. They then presented an improved process, confirmed in test structures and DRAM.

 

RF-SOI

18.4: Technology Pathfinders for Low Cost and Highly Integrated RF Front End Modules

C. Raynaud (Leti)

This paper highlights the challenges related to the increasing number of modes (GSM, WCDMA, LTE) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multimode multi–band RF Front End modules.

 

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This is the 1st post in a 3-part series. Part 2 (click here to  read it) of ASN’s IEDM ’14 coverage looks at papers covering SOI-based future device architectures.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

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