New interactive webinar on FD-SOI design posted by CMC


CMCMicro_28nmFDSOIA new interactive WebEx webinar on FD-SOI design sponsored by CMC Microsystems has been posted. Entitled Design and Characterization of Circuits and Devices in the ST 28nm Fully-Depleted Silicon-On-Insulator (FD SOI) (click here to view it), it features two presentations by University of Toronto professors based on their recent experiences with circuit design in the ST’s 28nm FDSOI CMOS technology. The webinar provides insights about circuit design, the technology’s unique features and capabilities, test devices measurement results relative to other technologies, and explores how this technology can be used in mm-wave, high-speed digital and silicon photonics applications.

Two mixed-signal transceivers implemented in ST’s 28nm FDSOI CMOS technology targeting these applications are summarized.  First, a low-power small-area transceiver compatible with the dense packaging technologies, such as silicon interposers, and operating up to 30Gb/s is presented.  Second, a 20Gb/s wireline receiver including a decision feedback equalizer (DFE) with digital adaptation logic and a digital CDR are required. Both designs include both high-speed analog blocks and synthesized digital logic using the technology’s standard cell libraries.

The webinar lasts about an hour all told, with 5-minute Q&A sessions following each presentation.  In the first minute or so there are a few technical snafus, but those are quickly resolved, so be patient: it’s worth the wait.

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