Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.
If you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.
Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.
Morning session: FD-SOI Workshop
FD-SOI foundry offer
- FD-SOI Advantages for Applications and Ecosystem — Philippe Magarshack, CTO, STMicroelectronics
- 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm — Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI
- [Title TBA] — Jamie Schaeffer, GlobalFoundries
FD-SOI IP offer
- Synopsys FD-SOI IP Solutions — Mike McAweeney, Sr. Director IP Product Sales, Synopsys
- FD-SOI: Ecosystem and IP Design — Amir Bar-Niv, Senior Group Director, Product Management, Design IP, Cadence
FD-SOI design experience
- [Title TBA] — N. Ben-Hamida, High speed Analog Design Manager, Ciena
- 28nm FD-SOI Design/IP Infrastructure — Shirley Jin, Sr. Director of Engineering, Verisilicon
Advantages and opportunities when designing with FD-SOI — Moderator: Dan Nenni, SemiWiki
- Marco Brambilla, Director of Engineering, Synapse
- Wayne Dai, Chairman, President & CEO, VeriSilicon
- Kelvin Low, Sr Director, Foundry Marketing, Samsung SSI
- Philippe Magarshack, CTO, STMicroelectronics
- Guntram Wolski, Cisco Systems
- Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator — Mike Noonen, Chairman & Co-founder, Silicon Catalyst
Afternoon session: More than Moore Forum
- RFSOI: Redefining Mobility and More in the Front-End – Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group
- Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers — Barend Van Liempd, PhD Researcher, IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,)
- RF SOI: from Material to ICs – an Innovative Characterization Approach — Mostafa Emam, CEO, Incize
- ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration — Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics
If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.
This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.
For the SF event – here’s the key information:
FD-SOI and RF-SOI Forum
- Friday, February 27th, 2015, 8am to 6pm
- Palace Hotel
- 2 New Montgomery Street, San Francisco, California, 94105 (USA)