The FD-SOI/RF-SOI Workshop in San Francisco last week was a huge success. Over 150 people from over 80 companies attended the all-day event. There were excellent presentations, animated Q&A sessions, and lots of networking going on over coffee, lunch and cocktails. It generated excellent press (click here to see the EETimes feature) and lots of activity on LinkedIn and Twitter.
Everyone agreed it was an outstanding day, with all the presenters emphasizing the value, availability and ramp of FD-SOI. Feedback from the presenters indicates that the workshop spurred a significant boost in interest and opportunities. As one participant noted, “This was very credible.”
If you didn’t make it to SF, we’ll cover the highlights in three ASN posts over the next few days (yes, it was that good!). Here in Part 1, we’ll cover the FD-SOI presentations. In Part 2, we’ll listen in on what was said during the panel discussion on FD-SOI. And in Part 3, we’ll take a look at the RF-SOI presentations. The actual presentations will all be posted shortly on the SOI Consortium website – keep checking back. But for now, here are some snapshots.
ST’s CTO Philippe Magarshack presented on FD-SOI Advantages for Applications and Ecosystem. He was very clear on the value proposition of FD-SOI, with multiple examples (and a tip of the hat to Soitec, which enabled ST with industrial FD-SOI substrate).
ST’s now got 18 active FD-SOI projects underway, he said. What’s driving it? FD-SOI is all about integration, he pointed out: digital, analog/mixed-signal and RF for starters. Beyond mobile, he cited three key application segments:
- networking infrastructure apps – thanks to low SER (soft error rates)
- IoT – especially for ultra-low voltage
- automotive – with a good summary of the value (see slide) and an example from video analytics (see slide).
He also provided a summary of the key design advantages:
- effective DVFS
- FBB (forward body bias) for dynamic transistor Vt (threshold voltage) control
- simple analog integration (a distinct advantage over bulk and FinFET)
- best SER (soft error rate)
With foundry partner Samsung and a complete design platform, the ecosystem is now in place, he concluded.
Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI had a very clear message on the FD-SOI foundry offer: they are in business!
In his presentation, 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm, he covered the technology migration history: scaling, material then structure innovation.
Driving home the message that 28nm will be a long-lived node, he said the PDK’s ready, foundry services are ready and they’re taking orders. (In fact, there was a whole team from Samsung there, answering additional questions and following up with prospective customers during the breaks.)
Kelvin showed manufacturability and reliability data, and PPA (power, performance, area) benchmarks (see slide).
For wearable apps, of course, low power is a must. Here, body biasing and low Vdd (supply voltage) are key, and again, 28nm FD-SOI shines (see slide).
EDA & IP
Next came excellent presentations by the EDA giants.
Mike McAweeney, Sr. Director IP Product Sales presented Synopsys FD-SOI IP Solutions.
Amir Bar-Niv, Senior Group Director, Product Management, Design IP at Cadence presented FD-SOI: Ecosystem and IP Design.
These were largely the same presentations given by these companies at the Tokyo FD-SOI workshop in December. Click here for ASN coverage of that event and details on those presentations.
Ben-Hamida, High Speed Analog Design Manager, Ciena presented the company’s view of the value of FD-SOI in their new 100Gb/s transceiver (see slide). He was very enthusiastic in his support of FD-SOI, and its ability to deliver on its promises.
And finally, Shirley Jin, Sr. Director of Engineering at design house Verisilicon presented very compelling benchmarking data on an ARM Cortex A-7 in her presentation, 28nm FD-SOI Design/IP Infrastructure (see slide). Shirley gave a similar presentation in Tokyo in December. Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. Her presentation presented extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.
Members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.
And stay tuned for Part 2 of ASN’s SF Workshop coverage – where we’ll cover the panel discussion, and the big news that Cisco’s on board with an FD-SOI chip of their own. Part 3 will cover the RF-SOI presentations, and the massive rate of innovation seen there.