Yes, Cisco Is Doing a 28nm FD-SOI Chip! (Part 2 of 3, SF Workshop: FD-SOI Panel Discussion)


More good news: Cisco is working on a 28nm FD-SOI chip. This additional boost to FD-SOI momentum was revealed during the Panel Discussion at the recent FD-SOI/RF-SOI Workshop in San Francisco. The EETimes coverage (which also revealed that Freescale’s putting its next-gen iMX7 microprocessor on 28nm FD-SOI – you can read it here) was quickly shared hundreds of times on LinkedIn.

SemiWiki’s Dan Nenni moderated the panel, which addressed Advantages and Opportunities when Designing with FD-SOI. Panelists included Marco Brambilla, Director of Engineering, Synapse Design; Wayne Dai, Chairman, President & CEO, VeriSilicon; Kelvin Low, Sr. Director, Foundry Marketing, Samsung SSI; Philippe Magarshack, CTO, STMicroelectronics; and Guntram Wolski, Principal Engineer at Cisco Systems.

In case you missed it, we covered the morning’s FD-SOI presentations in a previous post – click here to see it. As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience. In the next ASN post we’ll cover the RF-SOI presentations.

 

SF_FDSOI_panel
FD-SOI Panel Discussion during the 2015 San Francisco Workshop (left to right: Daniel Nenni , Semiwiki; Guntram Wolski, Cisco Systems; Philippe Magarshack, ST; Kelvin Low, Samsung SSI; Marco Brambilla, Synapse Design; Wayne Dai, VeriSilicon)

There was lots of anticipation going into the panel discussion, and it turned out to be one of the best parts of what was already a very successful day. There were lots of questions raised, and people commented afterwards that they appreciated that answers were candid and straightforward, while clearly being extremely supportive of FD-SOI.

Kelvin Low, Samsung

Kelvin was asked about the positioning of FD-SOI vs. FinFET at Samsung. He explained that there is no conflict, as each addresses a different set of needs. But 28FD: that’s a sweet spot, he reiterated.

He added that we need more FD-SOI seminars and workshops for the design community, to make people feel comfortable. (And those are in the works!) 

Guntram Wolski, Cisco

It was during this panel discussion that Guntram confirmed that Cisco is working on an FD-SOI based chip. Asked about what he sees as the value of FD-SOI technology, he responded:

  • at 28nm, you see a quarter of the leakage vs. bulk
  • it allows a simpler, fanless cooling system and flexibility in the form factor
  • power is so low with FD-SOI that they ended up being able to eliminate some other programs and pull them onto this ASIC
  • forward body bias enables multiple voltages

Asked why Cisco seems to be alone in adopting FD-SOI, he parried: because CIsco is a leader not a follower! He also confirmed that they’re working with all the foundry partners.

Wayne Dai, Verisilicon

Wayne said he sees IOT/wearables as big opportunity for FD-SOI, since they’re power sensitive apps. He commends ST for opening its IP and breaking the chicken-egg issue. He added that with multi-project wafer (MPW) runs from both Samsung and ST, there will be a lot of work on FD-SOI that will further demonstrate the value. Designing in FD-SOI is no different than bulk, he reminded the audience, adding that he’s expecting FD-SOI will be a three-node solution.

More questions, more answers

When someone asked if FD-SOI is so good, why is nobody manufacturing FD-SOI chips, Kelvin pointed out that there are three foundries in place. They have a solution for double patterning, the ecosystem is now in place, and Samsung will have a fully qualified foundry ready for risk production in March, so stay tuned !

Wayne added that 14FD can be better in many cases than FinFET, and Philippe reminded the audience that Sony is designing with FD-SOI. We’ve passed the critical point.

Asked about the value of FD-SOI in analog design, Philippe noted that quick switching of Vt with FD-SOI is 10x more efficient than bulk . When asked about 14nm cost, he responded that there are savings in limiting or removing double patterning in the backend and the middle of the line. Even with some remaining double patterning, there are 3-4 fewer than FinFET, and 10 fewer mask levels than FinFET.

When someone asked about timing and if it’s too late for 28FD with the leading edge already designing in 14nm FinFET, Kelvin responded that FinFET is sexy, but you need to look at the practical side and value of low power. Guntram said he saw many high volume and low power opportunities at 28nm.

Dan Nenni concluded with the reminder that on SemiWiki, for the last four years the #1 search term has been and continues to be “low power”.

The clear take-away message from the panel was that the FD-SOI solution is real!

In the next ASN post, we’ll review the SF workshop presentations on RF-SOI. (If you’re not already signed up for ASN’s email notifications of new posts, you can do it here.)

 

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