The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.
Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.
While paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.
Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.
Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.
There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.
There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about Ultra-Low Power.
During the Rump session we will debate about the What does IoT mean for semiconductor technology?
Scope of the conference:
The Committee will review papers submitted by May 18 in the three following focus areas of the conference:
Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.
Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.
3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.
Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.
Paper submission deadline: 18 May, 2015
Notification of acceptance: 07 June, 2015
Short course date: 5 October, 2015
Conference date: 5 – 8 October, 2015
More details are available on the S3S website.