Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

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Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.

ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.

Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?

Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.

ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?

SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.synapse_logo_300_ppi

ASN: At what point in the design process do you typically come in? What sorts of services do you offer?

SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.

ASN: What do you see as the advantages of FD-SOI?

SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.

SynapseDesign_FDSOI_v_bulk
An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.

We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.

ASN: Designers of what kinds of chips should be thinking about FD-SOI?

SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.

ASN: Why do they ultimately choose it? Why do they hesitate?

SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.

ASN: Are there special considerations designers should think about before starting a project in FD-SOI?

SynapseDesign_FDSOI_diffSB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.

ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?

SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.

Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.

ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?

SynapseDesign_FDSOI_summarySB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market

ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?

SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.

ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?

SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.

We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.

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Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.

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