Cadence tools enabled for GF 22FDX FD-SOI. Validated on ARM Cortex-A17. Reference flow available.

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Cadence has announced that its digital and signoff tools are now enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow (see press release here). GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of software-controlled body bias to manage power, performance and leakage needed to create next-generation chips for mainstream mobile, IoT and consumer apps. In addition, the ARM® Cortex®-A17 processor was used to validate the implementation flow with the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution.

Cadence collaborated with GF on the development of the PDK for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules. The digital implementation tools also support double-patterning aware parasitic extraction (PEX) and design for manufacturing (DFM).

“The 22FDX reference flow can enable customers to achieve real-time tradeoff between static power, dynamic power and performance to create innovative products,” said Pankaj Mayor, GF Biz Dev VP.

 

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