San Jose Symposium – Part 2 of 2 in an Epic Day for FD-SOI – the “Disruption Enabler” Right Through 7nm

This is part 2 (of 2) of ASN’s coverage of the epic FD-SOI Symposium in San Jose. In part 1 we looked at the exciting developments happening at 28nm (if you missed it, click here to read it now). Here in part 2, we’ll look at 22nm, covering the presentations by GlobalFoundries, ARM, VLSI Research and Sigma Designs. Again, the presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).

VLSI Research – FD-SOI is Enabler of Disruption

Dan Hutcheson, CEO of VLSI Research, has come around to FD-SOI. His excellent talk, “FD-SOI: Disruptive or Just Another Process” (click here to download it), concluded that FD-SOI is not disruptive – but it’s an enabler of disruption. The disruption is IoT, and it’s going to be a big one. To prepare for his talk, he did an informal survey of designers at a dozen top companies. Here are some of the things he heard:

  • Some companies are using FinFET for some chips and FD-SOI for others, depending on the market they’re targeting – either way, the technologies will co-exist. FinFETs were generally chosen for high-density chips from large companies with lots of money; FD-SOI by those who have time-to-market constraints, are looking to differentiate their products, appreciate the much lower NRE* costs, and that are going for power, reliability and analog advantages.

  • People see a future with FD-SOI – it’s not a one-trick process.

  • The design community is happy to be able to re-use many of their favorite techniques that were lost after the 130nm node.

  • Top target markets for FD-SOI are (by far) IoT, automotive and low-power, followed by analog/mixed-signal, networks, RF, low-end products, mobile, peripherals, MPU/GPU, image sensors and rad-hard.

Here are a couple of his slides that sum up the technical and business reasons people cited as reasons for going to FD-SOI:

(Courtesy: VLSI Research and SOI Consortium)
(Courtesy: VLSI Research and SOI Consortium)

Dan then made a video recapping his San Jose presentation – it’s awesome – click here to see it.

GlobalFoundries – Full House

The ballroom packed right out when GloFo VP Subramani Kengeri took the stage to present, “Enabling Next Generation Semiconductor Product Innovations with 22FDXTM.

The ballroom packed right out when GloFo VP Subramani Kengeri took the stage at the FD-SOI Symposium in San Jose. (photo credit: Adele Hars)
The ballroom packed right out when GloFo VP Subramani Kengeri took the stage at the FD-SOI Symposium in San Jose. (photo credit: Adele Hars)

In terms of energy efficiency, he explained, 0.4V is the minimum energy point for almost any technology – and FD-SOI gets you 0.4V. He then went on to reiterate the features of GloFo’s 22FDXTM Platform, the industry’s first 22nm FD-SOI:

  • Ultra-lower power with 0.4 volt operation

  • Software-controlled transistor body-biasing for innovative performance and power optimization

  • Delivers FinFET-like performance and better energy-efficiency at 28nm-like cost

  • Integrated RF: reduced system cost, and back-gate feature to reduce RF power up to ~50%

  • Integrated eNVM and RF enables lowest cost and smallest form-factor

  • Post-Silicon Tuning/Trimming for Analog/RF, SRAM and Power/Performance optimization

  • Enables innovative applications across mobile, IoT and RF markets

  • 70% lower power than 28HKMG, 20% smaller die than 28nm bulk planar

  • Lower die cost than FinFETs

He then gave lots of technical details (the whole presentation is now available for download from the SOI Consortium website – click here to get it). A key point is that FD-SOI will scale to 7nm. Here’s the slide that says it all:

(Courtesy: GlobalFoundries and SOI Consortium)
(Courtesy: GlobalFoundries and SOI Consortium)

Also, be sure to check out the Cadence presentation when it’s posted – it looks at the solid design methodology now in place.

ARM – now onboard!

Following a brief mea culpa acknowledging that ARM had been missing too long from the FD-SOI table, GM of the Physical Design group Will Abbey made it clear that they are now fully onboard. In his talk, “Realize the Potential of FD-SOI”, he said in comparisons between 22nm FD-SOI and 14nm FinFET, they see a lot of space for FD-SOI. Here’s his summary slide:

(Courtesy: ARM and the SOI Consortium)
(Courtesy: ARM and the SOI Consortium)

They are now looking at ways to further optimize back-biasing to decrease total power in block-level implementations. And yes, he said, you’ll get performance that’s close to FinFET.

Sigma Designs – IoT

Fabless innovator Sigma Designs is focused on the connected home (especially smart TV and media connectivity) and IoT. CEO Thinh Tran presented, “Enabling the Digital Connected World with FDSOI” – you can download it here.

If you really want to optimize for power efficiency, use FD-SOI and run at 0.4V, he advised. “I’m very excited about this,” he told the San Jose audience, adding that, “It’s especially good for RF.” Here’s his slide that explains why:

(Courtesy: Sigma Designs and SOI Consortium)
(Courtesy: Sigma Designs and SOI Consortium)

So, it was a great day in San Jose for 22nm and 28nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).

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