As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.
If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)
To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:
Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.
Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.
Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.
Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.
Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.
RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.
Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.
Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.
Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.
But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”
Next up: i.MX 8 for automotive +
At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.
We’ll cover it in an upcoming ASN blog, so stay tuned!
— By Adele Hars, ASN Editor-in-Chief