Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

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Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.

On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.

The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)

The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.  

(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)

Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.

FDSOI Short Overview and Advantages for Analog, RF and mmW Design – Andreia Cathelin, Fellow, STMicroelectronics, France

If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.

Summary slide from Professor Andreia Cathelin’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and ST)

She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology.  Then the focus  shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing.  For each category of circuits  (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass  filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.

Unique Circuit Topologies and Back-gate Biasing Scheme for RF, Millimeter Wave and Broadband Circuit Design in FDSOI Technologies – Sorin Voinigescu, Professor, University of Toronto, Canada.

Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics.  The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.

Summary slide from Professor Sorin Voinigescu’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and U. Toronto)

Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.

Design Strategies for ULV memories in 28nm FDS-SOI – Joachim Rodrigues, Professor, Lund University, Sweden

Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.

For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.

Summary slide from Professor Joachim Rodrigues’ course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Lund U.)

Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.

Energy-Efficient Processors in 28nm FDSOI – Bora Nikolic, Professor, UC Berkeley, USA

Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Summary slide from Professor Bora Nikolic’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and UC Berkeley)

Pushing the Envelope in Mixed-Signal Design Using FD-SOI – Boris Murmann, Professor, Stanford University, USA

If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.

Summary slide from Professor Boris Murmann’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Stanford U.)

Key Info About the FD-SOI Tutorial Day

  • Event: Designing with FD-SOI Technologies
  • Where: Samsung Semiconductor’s Auditorium “Palace”, San Jose, CA
  • When: April 14th, 2017, 8am to 3pm
  • Cost: $475
  • Organizer: SOI Industry Consortium
  • Pre-registration required – click here to sign up on the SOI Consortium website.

 

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