Body Biasing: It’s Not an Obligation, It’s an Opportunity. And Other Take-Aways from the FD-SOI Design Tutorial Day.

Over a hundred chip designers packed the room for the SOI Consortium’s recent FD-SOI Design Techniques Tutorial Day. Five professors and scientists from top institutions covered design techniques with real examples in digital, mixed-signal, analog, RF, mmW and ULV memory.

Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”

Many of the questions pertained to body biasing, which prompted STMicroelectronics Fellow and Professor Andreia Cathelin to state what may well have been the take-away of the day. “Body biasing is not an obligation,” she said. “It’s an opportunity.”

Q& A with the professors at the end of the FD-SOI Tutorial day. (Courtesy: SOI Consortium)

The tutorial, sponsored by both Samsung and GlobalFoundries, was hosted by Samsung at their San Jose headquarters.  But as this was a paying event, the presentations are only available to those who attended.  Having had the good fortune to attend, I can give you a quick recap of some of the highlights.

Analog, Mixed-Signal and mmW Design: The Overview

Professor Cathelin set the stage with a basic overview of FD-SOI design for analog, mixed-signal and mmW.

FD-SOI is a perfect match for the many up and coming SOCs that are often half analog and/or RF and mmW.  She explained how FD-SOI makes the analog designer’s life much easier (no small feat, since analog can seem rather like blackbox magic to those on the digital side).  FD-SOI improves: performance (even at high frequencies), noise, short device efficiency and brings in a new very efficient transistor knob through the Vt (threshold voltage) tuning range. She also explained and gave numerous real examples implemented in ST’s 28FDSOI on how:

  • forward body bias (FBB) can be used as a Vt tuning knob, giving the designer a very large Vt tuning range, both for analog/RF and mmW designs;
  • the improved analog performance gives you lower power consumption;
  • transistors can operate with decent design margins at L>Lmin.

For mmW design, the transistor should operate at Lmin, and hence you get excellence performance in terms of both transition frequency (Ft – set by the technology node) and maximum frequency (Fmax – what the designer can really get in the gain vs. speed trade-off). This can be conjugated with the fact that the back-end of line, despite the very fine nm node, takes advantage of the SOI features and brings in very decent quality factors.

For mixed-signal/high-speed design, she showed how and why FD-SOI gives you improved variability, a fantastic switch performance, and reduced parasitic capacitance. All these permit state of the art results in high-speed data converters, or, for example, lower frequency implementations which do not need any specific calibration for best in class linearity and ENOB (effective number of bits).

She also presented details on the CEA-Leti electrical models which are now the reference stand point (Leti-UTSOI2) for any FDSOI technology, and are implemented in several industrial Design Kits such those from ST.

RF, mmW and Broadband Fiber-Optic SOCs

Next on tap was a very lively talk with almost 60 slides by Professor Sorin Voinigescu of U. Toronto.  He focused on how to use the main features of FD-SOI for efficient design of RF, mm-wave and broadband fiber-optic SOCs.  We’re talking high-speed/high-frequency here, and he had real examples of chips fabbed in ST’s 28FDSOI and some simulated in GlobalFoundries’ 22FDX technology.

Last slide from Professor Voinigescu FD-SOI tutorial. (Courtesy: U.Toronto, SOI Consortium)

He examined layout issues and gave measurement tips and tricks, noting that there are a lot of things you can do in FD-SOI that you can’t do in bulk.  It’s also easier to get high linearity in FD-SOI – yet another reason that he really likes it.  Plus he sees it as competitive in terms of scaling even past 7nm.

ULV Memories

Professor Joachim Rodrigues of Lund University in Sweden (the largest university in Scandinavia) talked about Design Strategies for ULV memories in 28nm FD-SOI (ST’s FD-SOI technology). Noting that SRAMs eat a lot of area in an SOC, he first proposed a standard cell-based memory (SCM) in 28nm FD-SOI that cut memory area by 35% and reduced leakage by 70%.

Professor Joachim Rodrigues of Lund University presenting at the 2017 FD-SOI Design Techniques Tutorial Day in Silicon Valley (Courtesy: Lund U., SOI Consortium)

He then talked about other chips he and his team have presented at the world’s top chip conferences, including an ultra-low voltage (ULV) SRAM.  For that chip they lay claim to having the best write performance in ULV in sub-65nm (15MHz at 240mV), and the  best performing read capability across all technologies (30MHz at 240mV). In each case, he explained the fundamental design considerations, concepts and trade-offs.

Berkeley: 10 FD-SOI Chips – and Still Counting!

Professor Borivoje “Bora” Nikolic of UC Berkeley is an expert in body-biasing for digital logic. He and his team have designed ten chips in ST’s 28nm FD-SOI, and they’re now working on their 8th generation of energy-efficient SOCs. During his 90-slide (!) tutorial, Energy-Efficient Processors in 28nm FDSOI, he covered: digital logic (including implementation and adaptive tuning of cores for optimal energy efficiency); SRAM and caches (design scenarios and results compared to bulk); supply (generating, switching and analog assists); back bias (how it’s generated and how to use it). He finished with (60 slides of!) design examples and the results they got for power (including adaptive voltage scaling) and performance. He said to be on the lookout for upcoming publications on (even more!) chips, as well as new work on 22nm designs.

A page from Professor Nikolic’s tutorial on FD-SOI design for digital logic. (Courtesy: UC Berkeley, SOI Consortium)

Pushing the Mixed-signal Envelope

Even if you don’t know anything about mixed-signal design, you can walk away from an hour-long lecture by Professor Boris Murmann of Stanford with a good understanding of what it’s all about. In his talk, Pushing the Envelope in Mixed-Signal Design Using FD-SOI, he explained how a mixed-signal person thinks about FD-SOI, and how the different metrics and sweetspots vary depending on what you’re working on.  From there it was the deep dive, as he got into the heart of his talk: simulated transition frequency vs. gm/lD. He explained that while some things might seem counter intuitive (like long channels are more efficient for very low Ft requirements), it’s all related to electrostatics. It’s not yet well explained in the literature, he said, but it should be a big deal.  And he explained why with FD-SOI, you don’t have to design for the worst case. He then talked about where he sees things going – he sees a very bright future indeed for FD-SOI and analog as computing moves into very low-power neural networks. In the end, he said, it all boils down to the FD-SOI performance benefits with respect to better gate control. This translates into “significant improvements” for many mixed-signal/RF building blocks.

Professor Boris Murmann talks about FD-SOI for mixed-signal. (Courtesy: Stanford, SOI Consortium)

All in all, it was a really terrific day. BTW, this tutorial day followed a full-day FD-SOI Symposium in Silicon Valley. Click here to read about that.

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