Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.”

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Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.”

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving  the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving
the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, Dr. Colinge’s “…strong actions and enthusiastic beliefs were crucial for supporting the development of SOI technology.” One of the giants of the SOI community, Dr. Colinge is especially heralded in the industry for his seminal and continued work in multigate FETS (aka MuGFETs, a category that includes architectures such as FinFET and TriGate among others). Dr. Colinge and his work have been featured in many editions of ASN. Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari  (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).

New Edition of SOI Book by J.-P. Colinge

Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer.

The third edition of Professor Jean-Pierre Colinge’s book, Silicon-on-Insulator Technology: Materials to VLSI (ISBN: 1-4020-7773-4), is now available from www.springeronline.com.
A prolific author, Professor Colinge has written a book that covers the history of SOI technology and provides in-depth analyses of the physics, device properties and applications. It is recommended for both specialists and non-specialists, and as a textbook at the graduate level. •

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.

SOI Visionary Sorin Cristoloveanu Receives IEEE 2017 Andrew Grove Award

(Courtesy: Grenoble INP)

Sorin Cristoloveanu has been named the 2017 recipient of one of the IEEE’s highest honors, the Andrew Grove Award, for his “contributions to silicon-on-insulator technology and thin body devices.” An IEEE Fellow and highly regarded figure in the SOI community, Sorin is the Director of Research at the French National Center for Scientific Research (CNRS at IMEP-LAHC) in Grenoble, France.  

Here is how the IEEE describes him:

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits.

The Grove Award is given “for outstanding contributions to solid-state devices and technology”. In 2012, it was awarded to another SOI visionary, Jean-Pierre Colinge, “For contributions to silicon-on-insulator devices and technology.”

SOITEC and UCL boost the RF performance of SOI substrates

Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of wireless communication standards.

In 2003, UCL demonstrated the possibility of further improving the RF performance of HR-SOI substrates by minimizing or even eliminating the so-called parasitic surface conduction inherent in any oxidized silicon substrate [1]. UCL proposed a figure of merit, the effective resistivity, which helps compare the RF performance of various technological solutions as well as monitoring in-line the quality of fabricated substrates.

The effective resistivity accounts for the wafer inhomogeneities (i.e., oxide covering and space charge effects) and corresponds to the resistivity that a uniform (without oxide nor space charge effects) silicon wafer should have in order to sustain identical RF substrate losses. In other words, it is the value of the substrate resistivity that is actually seen by the coplanar devices.

Therefore, comparing the wafers in terms of their effective resistivity allows us to isolate the performance of the substrate by eliminating series losses and skin effect inside conductors. The interest of the effective resistivity as a factor of merit is not limited to the monitoring of the RF quality of the fabricated substrate but it is also a physical parameter which is used by RF designers to properly model the impact of the substrate.

A new substrate is born

Soitec and UCL have been working together to identify the technological opportunities to still further improve the high-frequency performance of commercially available HR-SOI substrates. Thanks to the introduction of an engineering substrate handle, Soitec can now provide a new flavor of HR-SOI called eSI, for enhanced Signal Integrity (see Figure 1) substrate (previously named Trap Rich) with a measured effective resistivity as high as 10 kOhm.cm [2].

New generation of HR-SOI substrate

Figure 1. A new generation of HR-SOI substrate: enhanced Signal Integrity (eSI) (Image courtesy of Soitec)

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along CPW lines and purely capacitive crosstalk similarly to quartz substrate. It has been demonstrated that the presence of a trap-rich layer does not alter the DC or RF behavior of SOI MOS transistors [3].

Besides the insertion loss issue along interconnection lines, the generation of harmonics in the Si-based substrates has been investigated. HR-SOI substrate presents reduced harmonics compared with standard SOI substrate and the introduction of engineering eSI substrate handle leads to harmonics levels well below the wireless communication systems [4] (see Figure 2).

Harmonic distortion along a 2,146 µm-long CPW line

Figure 2. Harmonic distortion along a 2,146 µm-long CPW line when a signal at 900 MHz is injected at the input for a trap-rich HR-SOI wafer from SOITEC. The specification (specs straight line) for the harmonic distortion corresponds to that of RF switches for GSM/EDGE transmitter modules [5].

The improvement of the HR-SOI substrate brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors, for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc.

Thanks to the introduction of eSIengineered substrate handle, the HR-SOI substrate can really be considered as a lossless Si-based substrate. eSI HR-SOI technology opens the path to further system integration in the Front End Module space as well as even more complex mixed-signal System-on-Chip (SoC).



A BIT OF HISTORYFor over 15 years, UCL’s Raskin research group has been developing high-frequency characterization techniques, which are today widely used by industry as well as other research teams. The group has been measuring advanced MOS devices (fully and partially depleted SOI transistors, FinFETs, Ultra-Thin Body and BOX (UTBB) devices, silicon nanowires, Junctionless multiple gate MOSFETs, etc.) from international research centers and companies.

UCL's Welcome platform

Figure 3. UCL’s Welcome platform: electrical characterization room of 350 m2.

The experimental platform known as “Welcome” at UCL (see video) is equipped with the latest electrical measurement equipment covering on-wafer measurements over a wide frequency range (DC up to 110 GHz) and temperature range (4K up to 300°C). UCL also has 1,000 m² in cleanroom facilities, including an SOI CMOS process (see Figure 4).

UCL's Winfab

Figure 4. UCL’s Winfab has 1000 m² of class M1 cleanroom facilities

In 1997, Prof. J.-P. Raskin presented pioneering work on the RF performance of HR-SOI substrates [6]. This paper demonstrated the great interest of HR-SOI substrates to reduce RF losses as well as the crosstalk in Si-based substrates.

In 2005, the team demonstrated the possibility creating HR-SOI substrates characterized with an effective resistivity as high as 10 kOhm.cm thanks to the introduction of a high density of traps at the BOX/HR-Si handle substrate [3]. Those traps originated from the grain boundaries in a thin (300 nm-thick) layer.

In 2011, with former PhD student Dr. Mostafa Emam, the team launched a spin-off company, Incize (www.incize.com), which offers RF electrical characterization services.


[1]    D. Lederer, F. Brunier, C. Desrumaux and J.-P. Raskin, “High Resistivity SOI substrates: how high should we go?”, IEEE International SOI Conference, Newport Beach Marriott Newport Beach, CA, USA, September 29 – October 2, 2003, pp. 50-51.

[2]    K. Ben Ali, C. Roda Neve, A. Gharsallah and J.-P. Raskin, “RF SOI CMOS technology on commercial trap-rich high-resistivity SOI wafer”, IEEE International SOI Conference – SOI’12, Napa, CA, USA, October 1-4, 2012, pp. 112-113.

[3]    D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity”, IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, November 2005.

[4]    C. Roda Neve and J.-P. Raskin, “RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 924-932, April 2012.

[5]    M. Carroll et al., “High-Resistivity SOI CMOS Cellular Antenna Switches,” CSIC 2009, October 2009, Greensboro, NC, pp. 1-4.

[6]    J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk reduction using SOI technology”, IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252-2261, December 1997.

SOI Luminaries Earn Top IEEE Honors

The IEEE is once again giving two of its most prestigious awards to some of the SOI and advanced substrate industry’s leading figures.

There are few greater honors in engineering than the IEEE  Technical Field Awards (TFAs). And once again, people who work in advanced substrates are among the recipients of two major awards: the Andrew S. Grove award and the Daniel E. Noble Award for Emerging Technologies.

The TFAs are awarded for contributions or leadership in specific fields of interest of the IEEE. The awards consist of a bronze medal, certificate, and honorarium. They are typically announced each summer, but the actual ceremonies take place over a year later, giving the recipients time to arrange their schedules to be there.

This explains why in the summer of 2011, the 2012 award winners were announced, while the ceremonies for the 2011 winners announced in the summer of 2010 are just being held now.

The Grove Award

The IEEE Andrew S. Grove Award honors its namesake’s lifetime achievements. It is sponsored by the IEEE Electron Devices Society, and presented to an individual for outstanding contributions to solid-state devices and technology.

As announced last year, the co-recipients of the 2011 IEEE Andrew S. Grove Award are Judy Hoyt and Eugene Fitzgerald.  Professor Hoyt is with the MIT Department of Materials Science. Eugene Fitzgerald is the Merton C. Flemings-SMA Professor of Materials Science and Engineering and head of The Fitzgerald Group at MIT.

Hoyt and Fitzgerald are cited for “seminal contributions to the demonstration of Si/Ge lattice mismatch strain engineering for enhanced carrier transport properties in MOSFET devices.” Their work on “strained” silicon and its application to SOI wafers is well-known in the advanced substrates community. (Professor Fitzgerald wrote about this work in ASN5, Summer 2006.)

The 2011 Grove Award will be presented at the 2011 IEEE International Electron Devices Meeting (IEDM), which takes place in December 2011 in Washington D.C., USA.

The IEEE has also announced that 2012 Grove award will feature another SOI luminary:  Jean-Pierre Colinge, Head of the Microelectronics Centre, Tyndall National Institute, Cork, Ireland. The award recognizes Dr. Colinge “For contributions to silicon-on-insulator devices and technology.”  He is heralded in the industry for his seminal and continued work in multigate FETS.  This paved the way for FinFET and TriGate architectures. The actual ceremony will take place at the end of 2012.  Dr. Colinge and his work have been featured in many editions of ASN.

Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari  (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).

The Noble Award

The IEEE Daniel E. Noble Award for Emerging Technologies honors Dr. Daniel E. Noble, Executive Vice Chairman of the Board emeritus of Motorola. It is given for outstanding contributions to emerging technologies recognized within recent years.

The 2011 Noble Award was given to Mark L. Burgener and Ronald E. Reedy for “basic research and development of silicon on sapphire technology culminating in high-yield, commercially viable integrated circuits”.  Dr. Burgener is vice president of advanced research and Dr. Reedy is the chief operating officer at Peregrine Semiconductor Corporation, San Diego, California.

In particular, the award recognizes their persistence and contributions in making silicon-on-sapphire (SOS) commercially viable for producing integrated circuits with improved speed, lower power consumption and more isolation compared to bulk silicon circuits.

The ceremony for the 2011 Noble Award took place during the IEEE/MTT-S International Microwave Symposium (MTT 2011) in June 2011 in Baltimore, MD, USA.

This summer, the IEEE also announced the winner of the 2012 Noble award: Subramanian S. Iyer, for “the development and implementation of embedded DRAM technologies.” Dr. Iyer is Distinguished Engineer & Chief Technologist, Semiconductor Research & Development Center, IBM Systems & Technology Group. He wrote about therole of SOI in “eDRAM” technology in ASN6 (December 2006). The technology is now at the heart of IBM’s latest offerings.

On the Leading Edge

Key advances in transistor research start on SOI.

SOI has always been the substrate of choice to explore new silicon device concepts and structures. The full dielectric isolation of the silicon allows one to dismiss the sometimes complex junction isolation schemes used in bulk silicon. The possibility of making devices in thin silicon films has enabled a number of new operation modes such as: volume inversion, where the bulk of the silicon film is inverted; and accumulation-mode operation, in which the channel region has the same doping polarity as the source and drain.

It is only afterwards that bulk processes are devised to mimic the original SOI device: the bulk FinFET is a bulk silicon version of the DELTA device or the SOI FinFET; and the double-gate silicon-on-nothing device is a version of the gate-all-around FET that does not use SOI wafers.

FD-SOI: the trigger point?

Another key advantage of SOI is the possibility of fully depleting a device. This is obviously not possible in bulk silicon.

Fully depleted MOSFETs have long been known to be “ideal” transistors, featuring optimal subthreshold slope, optimal body effect, better current drive, transconductance and linearity than bulk transistors, and lower soft error rate. They also show lower leakage currents and threshold voltage variation when temperature is increased.

Yet, these devices have not yet been widely adopted by industry. Recent findings by Leti and other research groups show that transistor parameter variability can be reduced when using FD-SOI. This may be the trigger point that may convince the industry.

Junctionless SOI nanowire transistor (Courtesy: Tyndall National Institute)

We can add to the picture the fact that “remote” or “virtual” doping can be achieved using the “back-gate mirror doping” technique, in which forming a doping profile in the substrate below a thin BOX is found to “induce” a similar doping profile in the thin-film SOI device above the BOX.[1] This effect can be used to modulate the virtual doping concentration in channels that are, otherwise, lightly doped or undoped.

The other side of doping

But there are also very exciting results at the other side of the doping concentration scale. The recently published junctionless transistor is a heavily doped silicon SOI nanowire pi-gate FET with no junctions nor doping concentration gradients.[2] The doping concentration is as high as what is normally used in source and drain.

Interestingly, the use of very high doping concentrations eliminates the problem of doping fluctuations just as well as the use of undoped channels does. Having no junctions is an obvious advantage when you are considering sub-22nm nodes. It also greatly facilitates the use of semiconductor materials other than silicon.
After having worked on SOI devices for the better part of the last 30 years, I still find it is a fascinating field of research, especially if one considers the advent of quantum effects in nanoscale SOI devices.

[1] “Back-gate Mirror Doping for Fully Depleted Planar SOI Transistors with Thin Buried Oxide”, R. Yan et al., 2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), April 2010
[2] “Nanowire transistors without junctions”, J-P Colinge, et al., Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010

IEEE SOI Conference

October 2008, New Paltz, NY, USA

Researchers from the world over gathered at the beautiful Mohonk Mountain House in upstate New York this fall to listen to over 50 excellent presentations. Hot topics included memory, reliability and optimization. A selection of some of the best follows below, with links embedded for easy access to the abstracts.


• 7.3: Capping-Metal Gate Integration Technology for multiple-VT CMOS in MuGFETs

A. Veloso, L. Witters, M. Demand, I. Ferain1, N. J. Son, B. Kaczer, Ph. J. Roussel, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer, S.Biesemans, M. Jurczak (IMEC, Samsung, K. U. Leuven)

MuGFETs with caps sandwiched in-between 2 metals (TiN or TaN) in the gate stack were studied for multiple-VTs CMOS applications, resulting in additional understanding on the caps diffusion mechanism, reliability behavior and integration implications. This addresses concerns with regard to the tuning options for narrow fins. It is compatible with 3D device architectures and suitable for high-density circuits at sub-32nm nodes.


• P6.1: Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low Power Applications

D. Bol, R. Ambroise, D. Flandre , J.-D. Legat (U. Catholique de Louvain)

The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional Vdd and static energy. This makes FD SOI with metal gate a strong candidate for sub-45nm robust and energy-efficient subthreshold circuits.

• 1.1: Variability and power management in sub-100nm SOI technology for reliable high performance systems

Das, Koushik; Bernstein, Kerry; Burns, Jeff; Gebara, Fadi; Shih-Hsien Lo,; Nowka, Kevin; Rao, Rahul; Rosenfield, Michael (IBM)

Going forward, variability and power management are very big and inter-related issues. This paper gives an overview of the power/variability challenges in sub-100nm CMOS. It illustrates several circuit, EDA and system level reliability techniques for building robust low-power systems. Finally, to optimally design extremely dense, multi-core chips with billions of transistors, the authors emphasize the need for an approach integrating technology development, VLSI design, design automation tools and micro-architecture.

• 1.2: SOI-enabled MEMS processes lead to novel mechanical, optical, and atomic physics devices

Herrera, G. V.; Bauer, Todd; Blain, M. G.; Dodd, P. E.; Dondero, R.; Garcia, E. J.; Galambos, P. C.; Hetherington, D. L.; Hudgens, J. J.; McCormick, F. B.; Nielson, G. N.; Nordquist, C. D.; Okandan, M.; Olsson, R. H.; Ortiz, K.; Platzbecker, M. R.; Resnick, P.J.; Shul, R. J.; Shaw, M. J.; Sullivan, C. T.; Watts, M. R. (Sandia)

Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers in the mid-1990s to develop a radiation-hardened semiconductor process for sub-0.5μm geometries. The expertise they developed opened opportunities to improve other technologies. This paper presents a high-level description of their SOI process technologies that have enabled a novel devices and products, including an accelerometer, RF MEMS microresonators and contacting switches, integrated optics (low-loss Si waveguides, the smallest and lowest power micro-ring modulators and thermo-optic phase modulators/switches), and ion traps for quantum computing (along with other atomic physics device examples).

• 2.1: Will SOI have a life for the low-power market?

Cai, Jin; Ren, Zhibin; Majumdar, Amlan; Ning, Tak H.; Yin, Haizhou; Park, Dae-Gyu; Haensch, Wilfried E. (IBM)

This paper looks at the key challenges for SOI CMOS to achieve sub-100pA/µm leakage current, which is required for low-standby power applications. Recent 45nm data illustrates the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, the authors identify several unique SOI opportunities that can broaden its appeal to the low power market.

• 3.1: Floating Body Cell Memory for 16-nm Technology with Low Variation on Thin Silicon and 10-nm BOX

U. E. Avci, I. Ban, D. L. Kencke, and P.L.D. Chang (Intel)

The authors demonstrate a scaled planar FBC technology with undoped-body featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. They predict this FBC scaling will be feasible at the 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

• P7.2: Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

Makosiej, Adam; Nasalski, Piotr; Giraud, Bastien; Vladimirescu, Andrei;Amara, Amara (Technical U. Lodz, ISE Paris, UC Berkeley, Leti)

This paper describes two novel sub-32nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10–15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.

• 5.1: High Speed Photonics on an SOI platform

J. Basak, L. Liao, A. Liu, Y. Chetrit, H. Nguyen, D. Rubin, and M. Paniccia (Intel, Numonyx)

This paper talks about the developments in silicon photonic devices that exploit the inherent high refractive index contrasts achievable on an SOI platform. It focuses on the optical modulator that has been designed for speeds up to 40Gbps. It also describes the design and performance of a photonic integrated transmitter chip, which has been demonstrated to transmit at an aggregate data rate of 200Gbps.

• 5.6: A 10-Bit Current-Steering FinFET D/A Converter

M. Fulde, F. Kuttner, K. v. Arnim, B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, M. Becherer, D. Schmitt-Landsiedel, G. Knoblinger (Infineon, Technical U. Munich, IMEC)

The integration of A/D and D/A converters is very important for SoC applications. The authors present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current-steering D/A converter are shown. The achieved performance proves the ability of recent FinFET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching and analog behavior of FinFETs enables reduced circuit area compared to planar designs.

• 6.2: SOI-GeOI hybrid substrates elaboration by Ge condensation: Process and electrical properties

Nguyen, Q.T.; Damlencourt, J.F.; Vincent, B.; Loup, V.; Le Cunff, Y.; Gentil, P.; Cristoloveanu, S. (IMEP-INP, CEA-Leti)

The authors report on the successful fabrication of hybrid SOI-GeOI wafers. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole-mobility in Ge islands and high electron-mobility in Si islands. The data confirms that hybrid wafers are attractive for co-integrating pMOSFETs in Ge and nMOSFETs in Si.

• 6.5: Characterization of a Three-Dimensional SOI Integrated-Circuit Technology

C.K. Chen, N. Checka, B.M. Tyrrell, C.L. Chen, P.W. Wyatt, D.R.W. Yost, J.M. Knecht, J.T. Kedzierski, C.L. Keast; (Lincoln Labs, MIT)

Lincoln Labs established a 3D IC technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. 3DIC technology in the most recently completed run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers. This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determining the impact of 3D vias on ring oscillator performance, and demonstrating functionality of single and multi-tier circuits of varying complexity. The work was sponsored under a DARPA/Air Force contract.

• 7.2: Twin Silicon Nanowire FET (TSNWFET) On SOI With 8 nm Silicon Nanowires and 25 nm Surrounding TiN Gate

D.-W. Kim, M. Li, K. Hwan Yeo, Y. Y. Yeoh, S. D. Suk, K. H. Cho, K. Oh, W.-S. Lee (Samsung)

This paper reports fabrication of twin silicon nanowire FETs on SOI with down to 25-nm TiN surrounding the gate and 8-nm silicon nanowires with high manufacturability. Improved device reliability includes the reduction of junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. High performance is also obtained: 1124μA/μm and 1468μA/μm at off current of 1nA/μm for NMOS and PMOS, respectively.

• 7.5: Optimizing FinFET geometry and parasitics for RF applications

Kranti, Abhinav; Raskin, Jean-Pierre; Armstrong, G. Alastair (Queen’s U. Belfast, U. Catholique de Louvain)

This paper gives a detailed analysis on the impact of parasitic capacitances/resistances and fin geometry in FinFETs for RF applications. RF FinFETs should be designed with Tfin/Lg of 0.6 and AR of 3, along with minimal fin spacing of 50 nm to achieve higher ƒT and ƒMAX values. Although FinFET will always exhibit higher parasitics than an equivalent planar technology, reduction of RSD to ITRS target specification, together with a minimal fin spacing Sfin, results in significant improvement in RF figures of merit.

• 8.1: Scaling and soft errors: Moore of the same for SOI?

Alles, M. L.; Ball, D. R.; Massengill, L.W.; Schrimpf, R. D.; Reed, R. A.;Bhuva, B. L. (Vanderbilt U.)

The continued path on Moore’s Law has increased the concern about soft errors, even in terrestrial applications. Multiple device (multiple bit) interactions and upsets are now one of the major challenges of analysis and mitigation in bulk CMOS devices. This is perhaps the major advantage for SOI with respect to single event effects. New SOI devices, including the MugFETS and ZRAMs, present opportunities for additional detailed study of single event effects as the devices approach the mainstream. One of the interesting aspects of the ZRAM is the difference in data state vulnerabilities compared to the conventional bulk DRAMs. This paper examines single-event effects and implications for SOI CMOS.

• 8.3: Novel SOI-Specific Circuit Form High-Speed Radiation-Hardened Memories

T.P. Haraszti1, R. Pancholy, J. Choma, R. Schober, K. Hunt; (Microcirc, USC, NanoPower, USAF Research Lab)

In all of the seven main memory components, the use of the novel SOI-specific sense amplifiers, memory-cells, and logic gates, evinced exceptionally speedy operations. This made possible fabrication and tests of complete memories which feature 2.2 GHz operational speed, 10−l2 error/bit/day and 1 Mrad total dose hardness. The SOI memories can indeed provide substantially faster operations than their best bulk counterparts do.

• 8.5: Double Thick Copper BEOL in Advanced HR SOI RF CMOS Technology: Integration of High Performance Inductors for RF Front End Module

C. Pastore, F. Gianesello, D. Gloria1, E. Serret, P. Bouillon, B. Rauber, Ph. Benech (STMicroelectronics, IMEP/LAHC)

High-performance on-chip inductors are key RF passive components for most RF circuits. This paper reports on a state-of-the-art inductor integrated in an advanced high resistivity (HR) SOI RF CMOS technology, using a double 3-μm thick back-end-of-the-line (BEOL) module. The inductor performance is comparable to those obtained in dedicated passive component technologies (Integrated Passive Device (IPD) on glass or RF substrates): a quality factor Q greater than 30 and current capability up to 57 mA/μm @ 125 °C. The results pave the way to the integration of the whole RF front-end module (which is currently served by GaAs technologies) in an advanced HR SOI CMOS technology.

• 8.6: High temperature RF behavior of SOI MOSFETs for low-power low-voltage applications

Emam, M.; Vanhoenacker-Janvier, D.; Anil, K.; Ida, J.; Raskin, J.-P. (U. Catholique Louvain, Oki Electric)

At Zero-Temperature-Coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for Low-Power Low-Voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and Partially Depleted SOI MOSFETs with and without body contact are analyzed.

• 9.2: Impact of surface and buried interface passivation on ultrathin SOI electrical properties

G. Hamaide, F. Allibert, S. Cristoloveanu (Soitec, IMEP-INPG MINATEC)

The thickness dependence of mobility in state-of-the-art SOI wafers is essentially an artefact due to the vertical field, stemming from surface charges and increasing as the film gets thinner. Various passivation treatments were used and combined; their impact on top surface and buried interface quality was studied separately. Excellent mobility values, above 650 cm2V−1s−1 for electrons and 200 cm2V−1s−1 for holes were achieved after FGA.

• 9.3: High-k/metal Gate GeOI pMOSFET: Validation of the Lim&Fossum Model for Interface Trap Density Extraction

K. Romanjek, C. Le Royer, A. Pouydebasque, E. Augendre, M. Vinet, C. Tabone, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, L. Clavelier, X. Garros, G. Reimbold, N. Daval, F. Boulanger, S. Deleonibus; (CEA-LETI/MINATEC, Soitec).

The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of Germanium-On-Insulator pMOSFETs is shown using the Lim&Fossum model historically developed for fully depleted SOI devices. This method can be used as a simple and efficient way to monitor the influence of the process on top and bottom interface trap densities and can be used as a process optimization qualifier for GeOI devices.

• 10.1: Ultra-scaled Z-RAM cell

S. Okhonin, M. Nagoga, C.-W. Lee, J.-P. Colinge, A. Afzalian, R. Yan, N. Dehdashti Akhavan, W. Xiong, V. Sverdlov, S. Selberherr, C. Mazure (Innovative Silicon, Tyndall National Institute, Texas Instrument Inc., TU Vienna, Soitec)

Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.

Industry Experts Contribute to New Book on MuGFETs

Jean-Pierre Colinge brings together work from top researchers in physics, design and fabrication of advanced devices.

Jean-Pierre Colinge has edited a recent addition to Springer’s Integrated Circuits and Systems Series, entitled FinFETs and Other Multi-Gate Transistors. A well-known figure in the SOI world, Colinge brings together chapters contributed by some of the world’s leading experts on multigate FET (MuGFET) technology. In addition to Colinge, contributors include Wade Xiong of TI, Olivier Faynot of CEA-LETI (both of whom also have articles in this current edition of ASN), Chenming Hu of UC Berkeley, and Gerhard Knoblinger of Infineon. Read More

Conference Proceedings

International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
(April 2007):

Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI), Che-Hua Hsu, Weize Xiong, Chien-Ting Lin, Yao-Tsung Huang, Mike Ma1, C.R Cleavelin, Paul Patruno, Mark Kennard, Ian Cayrefourcq, Kyoungsub Shin, Tsu-Jae King Liu (UMC, Texas Instruments, Soitec, UC Berkeley), pp. 174-175.

Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies.  K. Schruefer, K. von Arnim, C. Pacha, J. Berthold, C. R. Cleavelin, T.Schulz, W. Xiong, and P. Patruno(Infineon Technologies, Texas Instruments, ATDF, Soitec)

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL, Collaert, R. Rooyackers, G. Dilliwaya, V. Iyengar, E. Augendre, F. Leys, I. Cayrefourq, B. Ghyselen, R. Loo, M. Jurczak and S. Biesemans (IMEC, University of Surrey, K.U. Leuven, ESAT-INSYS, University of North Carolina at Charlotte, Soitec)  , pp. 176-177.

ECS, Silicon-on-Insulator Technology and Devices 13, ECS Transactions, Volume 6, Issue 4, 2007 (Editors: G. Celler, S. Bedell, S. Cristoloveanu, F. Gamiz, B.Nguyen, Y. Omura):

Embedding Device Solutions in Engineered Substrates, Carlos Mazuré (Soitec), DOI: 10.1149/1.2728835.

SOI Metrology and Characterization in Modern Wafer Production, Oleg Kononchuk, F. Brunier, and M. Kennard (Soitec).  DOI: 10.1149/1.2728865.

Evaluation of different etching techniques in order to reveal dislocations in thick Ge layers, A. Abbadie, J.M. Hartmann, C. Deguet, L. Sanchez, F. Brunier, and F. Letertre (Soitec, CEA-LETI).

A Chromium-free Defect Etching Solution for Application on SOI, J. Mähliß, A. Abbadie and B. O. Kolbesen (JWG University, Soitec).

Complementary Single-Crystal Silicon TFTs on Plastic, H.-C. Yuan, Z. Ma, C. S. Ritz, D. E. Savage, M. G. Lagally, and G. K. Celler (U.Wisconsin, Soitec).

Instability of Threshold Voltage of Flexible Single-Crystal Si TFTs, H. Pang, H.-C. Yuan, M. G. Lagally, G. K. Celler (U.Wisconsin, Soitec).

Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications, Weize W. Xiong, C. Rinn Cleavelin, Che-Hua Hsu and Mike Ma, Klaus Schruefer, Klaus Von Arnim, Thomas Schulz, Ian Cayrefourcq, Carlos Mazure, Paul Patruno, Mark Kennard, Kyoungsub Shin, Sun Xin, and Tsu-Jae King Liu, Karim Cherkaoui, and J.P. Colinge (Texas Instruments, UMC, Infineon, Soitec, UC Davis, Tyndall National Institute).

VLSI Symposium, June 11-14, 2007, Kyoto,Japan

Fully Integrated VLSI CMOS and Photonics, (Plenary talk by C.Gunn, Luxtera)
The future direction of photonics, on SOI and integrated into CMOS circuits. As an example, a 40 Gbps transceiver is demonstrated.

SOI SRAM by ABC-technology for 32nm, (Y.Hirano, Renesas)
The active-body-biased (ABC) structure, where the body-bias is controlled through well-contact is applied to the SRAM cell. It was shown that ABC enhanced the static-noise-margin (SNM) by 27% for 32nm node, and 49% for 22nm node.

Multiple Stress Memorization in Advanced SOI CMOS Technologies, (A.Wei, AMD)
A new stress memorization technique (SMT)featuring source/drain amorphization plus low temperature was presented. It has the additive effect to the conventional high-temperature RTA-induced SMT in terms of drain current enhancement. It was ascribed to the stress localization to the source/drain regions, as a result of amorphization implantation.

Scalability of Direct Si Bonding (DSB) for 32nm node, (H.Yin, IBM)
Defect elimination at STI boundary is discussed with optimization of process sequence, (110) Si thickness, and 45-degree rotated (100) substrate. It is concluded that it is scalable down to 22nm with these countermeasures.

IEEE International SOI Conference (October 1-4, 2007, Indian CA,USA)

BEST PAPER AWARD:  High performance, highly reliable FD/SOI I/O MOSFETS in contemporary high-performance PD/SOI CMOS, V.P. Trivedi et al (ASTS, TSO, Freescale).

45nm SOI and beyond – getting to a general purpose technology, Subramanian Iyer (IBM plenary).

SOI based technology for smart power applications, P. Wessels (NXP plenary).

Analog and RF SOI circuits for low poer or harsh environment applications, L. Demeus (CISSOID plenary).

65nm CMOS Bulk to SOI comparison, J.L. Pelloie et al (ARM, UMC).

Integrated Inductors in HR SOI CMOS technologies:  on the economic advantage of SOI technologies for the inegration of RF applications, F.Gianesello et al (STMicroelectronics, CEA-LETI).

Linear cellular antenna switch for hightly-integrated SOI front-end, T. McKay et al (RFMD).

Physical IP for SOI design infrastructure, JL Pelloie (ARM, invited).

A Plasma Damage Mitigation Concept for SOI Technologies: Lightning Rods, M.Pelella et al (AMD).

Dual Silicide SOI CMOS Integration with Low-Resistance PtSI PMOS Contacts, S. Zollner et al (Freescale).

A Novel Two-Transistor Floating Body Memory Cell, J. Fossum et al (U.Florida, Freescale).

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET, W. Xiong et al (Texas Instruments, Central R&D, Soitec, Tydall National Institute, UC Davis).

Evaluation of FinFET RF Building Blocks, G. Knoblinger et al (Infineon, Technical U.Munich, IMMS, Texas Instruments, Soitec).

Study of Fin Profiles and MuGFETs built on SOI wafers,  P. Patruno et al (Soitec, CEA-LETI, Texas Instruments, Central R&D, UMC, Tyndall National Institute).

High hole mobility GeOI pMOSFETs with high K/metal gate on Ge condensation wafers, L. Clavelier et al (CEA/LETI-Minatec, STM, IMEP/INPG-Minatec).

Insights Into Gate-Underlap Design in FinFETs for Ultra-Low Voltage Analog Performance, A. Kranti et al (Northern Ireland Semiconducytor Research Centre, School of Electrical and Electronic Engineering).

Technology-Based FOM for High Voltage LDMOSFETs-Proof of Value of SOI in Power ICs, M.M. Iqbal et al(Engineering Dept, Cambridge University).

RF Lopwer NLDMOS Technology Transfer Strategy from 130nm to, the 65nm Node on thin SOI, O. Bon et al (STM, University de Toulouse, CEA-LETI).

Gate Controleed Bipolar Action in Ultrathin Body Dynamic-Threshold SOI MOSFET, Y Omura et al (Kansai University).

65nm CMOS Bulk to SOI comparison, R. Mishra et al (GeorgeMason University, IBM).

Circuit Performance Optimization in Advanced PD-SOI CMOS Development, W.T. Chiang et al (UMC, ARM).

3D Stacked Channels: How series resistances can limit 3D Devices Performance, E. Bernard et al (CEA-LETI, STM, NXP, INLINSA).

Innovative approach to drive floating body Z-RAM embedded momory to 32nm and beyond, D. Fisch et al (Innovative Silicon).

Analysis of Sensing Margin in Silicon-on-ONO (SOONO) Devive for capacitor-less RAM Application, E. J. Yun et al (Samsung).

SOI Devices and RO on Thin Dielectric Membrances for Pressure Sensing Applications, B. Olbrechts et al (Universite Catholique de Louvain, Concordia University).

Flexfet™: Independently-Double-Gated SOI Transistor with Variable Vt and 0.5V Operation Achieving near Ideal Subthreshold Slope, D. Wilson et al (American Semiconductor Inc., Boise State University, Tennessee Tech University).

Multi-Gate SOI MOSFET operations in harsh environments, W.Xiong et al, (TI invited, Central R&D, Infineon, Tyndall, UC Davis, Soitec).

Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs, J. Song et al (UC San Diego, TI, Central R&D,UMC, Soitec).

SiGe and Ge Material, Processing and Devices Vol 3 N°7:

In situ HL etching and selective epitaxial growth of doped Ge for formation of recessed sources drains. J.M. Hartmann et al (CEA-LETI, STMicroelectronics).

Nanoscaled MOSFET transistors on Strained Si, SiGe & Ge layers: some integration and electrical features. T Ernst et al (CEA-LETI/IMEP).

Channel material Innovation for continuing the historical MOSFET Performance Increase. D.A. Antoniadis, A. Khakifirooz, I.Aberg, J.L.Hoyt (MIT).

Note: for more papers from last year’s ECS meeting, see the PaperLinks in ASN6.


AlGaN/GaN HEMTs on Epitaxies Grown on Composite Substrate, V. Hoel, S. Boulay, H. Gerard, V. Raballand, E. Delos, J.C. De Jaeger, M.A.Poisson, C. Brylinski, H. Lahreche, R.Langer, P.Bove (I.E.M.N, U.M.R-C.N.R.S, Alcatel-Thales III-V Lab, Picogiga International).  European Microwave Integrated Circuits Conference 2007 (Formerly GAAS®), Munich, 8-10 October 2007.

Nanomechanical Properties of strained Silicon-on-Insulator (SOI) Films epitaxially grown on
Si1-xGex and Layer Transferred by Wafer Bonding, Nathanael Miller, Kandabara Tapily, Helmut Baumgart, A. A. Elmustafa, George K. Celler and Francois Brunier (Old Dominion University, The Applied Research Center-Jefferson Lab, Newport News, VA, Soitec), MRS Proc. April 2007.

Flexible RF/Microwave Switch-PIN Diodes using Single-Crystal Si-Nanomembranes, H. Yuan, Z. Ma,  G. K.Celler, Proc. IEEE MTT-S  Intern. Microwave Symposium 2007 (Honolulu, Hawaii) paper WEP1B-11. (U.Wisconsin-Madison, Soitec)

A Merged MuGFET and planar SOI Process technology, Andrew Marshall, C. Rinn Cleavelin, Weize Xiong, Christian Pacha, Gerhard Knoblinger, Klaus Von Armin, Thomas Schulz, Klaus Schruefer, Ken Matthews, Wolfgang Molzer, Paul Patruno, Christian Russ.  IEEE International SOC Conference (September 26-28, 2007, Hsinchu, Taiwan).  (TI, Infineon, ATDF, Soitec).