Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, Dr. Colinge’s “…strong actions and enthusiastic beliefs were crucial for supporting the development of SOI technology.” One of the giants of the SOI community, Dr. Colinge is especially heralded in the industry for his seminal and continued work in multigate FETS (aka MuGFETs, a category that includes architectures such as FinFET and TriGate among others). Dr. Colinge and his work have been featured in many editions of ASN. Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).
Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer.
The third edition of Professor Jean-Pierre Colinge’s book, Silicon-on-Insulator Technology: Materials to VLSI (ISBN: 1-4020-7773-4), is now available from www.springeronline.com.
A prolific author, Professor Colinge has written a book that covers the history of SOI technology and provides in-depth analyses of the physics, device properties and applications. It is recommended for both specialists and non-specialists, and as a textbook at the graduate level. •
If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.
The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.
One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.
This year, papers in the following areas have been solicited:
Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.
EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.
And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).
Grenoble the first week of April 2019 is clearly the place to be.
Sorin Cristoloveanu has been named the 2017 recipient of one of the IEEE’s highest honors, the Andrew Grove Award, for his “contributions to silicon-on-insulator technology and thin body devices.” An IEEE Fellow and highly regarded figure in the SOI community, Sorin is the Director of Research at the French National Center for Scientific Research (CNRS at IMEP-LAHC) in Grenoble, France.
Here is how the IEEE describes him:
A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits.
The Grove Award is given “for outstanding contributions to solid-state devices and technology”. In 2012, it was awarded to another SOI visionary, Jean-Pierre Colinge, “For contributions to silicon-on-insulator devices and technology.”
The IEEE is once again giving two of its most prestigious awards to some of the SOI and advanced substrate industry’s leading figures.
There are few greater honors in engineering than the IEEE Technical Field Awards (TFAs). And once again, people who work in advanced substrates are among the recipients of two major awards: the Andrew S. Grove award and the Daniel E. Noble Award for Emerging Technologies.
The TFAs are awarded for contributions or leadership in specific fields of interest of the IEEE. The awards consist of a bronze medal, certificate, and honorarium. They are typically announced each summer, but the actual ceremonies take place over a year later, giving the recipients time to arrange their schedules to be there.
This explains why in the summer of 2011, the 2012 award winners were announced, while the ceremonies for the 2011 winners announced in the summer of 2010 are just being held now.
The IEEE Andrew S. Grove Award honors its namesake’s lifetime achievements. It is sponsored by the IEEE Electron Devices Society, and presented to an individual for outstanding contributions to solid-state devices and technology.
As announced last year, the co-recipients of the 2011 IEEE Andrew S. Grove Award are Judy Hoyt and Eugene Fitzgerald. Professor Hoyt is with the MIT Department of Materials Science. Eugene Fitzgerald is the Merton C. Flemings-SMA Professor of Materials Science and Engineering and head of The Fitzgerald Group at MIT.
Hoyt and Fitzgerald are cited for “seminal contributions to the demonstration of Si/Ge lattice mismatch strain engineering for enhanced carrier transport properties in MOSFET devices.” Their work on “strained” silicon and its application to SOI wafers is well-known in the advanced substrates community. (Professor Fitzgerald wrote about this work in ASN5, Summer 2006.)
The 2011 Grove Award will be presented at the 2011 IEEE International Electron Devices Meeting (IEDM), which takes place in December 2011 in Washington D.C., USA.
The IEEE has also announced that 2012 Grove award will feature another SOI luminary: Jean-Pierre Colinge, Head of the Microelectronics Centre, Tyndall National Institute, Cork, Ireland. The award recognizes Dr. Colinge “For contributions to silicon-on-insulator devices and technology.” He is heralded in the industry for his seminal and continued work in multigate FETS. This paved the way for FinFET and TriGate architectures. The actual ceremony will take place at the end of 2012. Dr. Colinge and his work have been featured in many editions of ASN.
Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).
The IEEE Daniel E. Noble Award for Emerging Technologies honors Dr. Daniel E. Noble, Executive Vice Chairman of the Board emeritus of Motorola. It is given for outstanding contributions to emerging technologies recognized within recent years.
The 2011 Noble Award was given to Mark L. Burgener and Ronald E. Reedy for “basic research and development of silicon on sapphire technology culminating in high-yield, commercially viable integrated circuits”. Dr. Burgener is vice president of advanced research and Dr. Reedy is the chief operating officer at Peregrine Semiconductor Corporation, San Diego, California.
In particular, the award recognizes their persistence and contributions in making silicon-on-sapphire (SOS) commercially viable for producing integrated circuits with improved speed, lower power consumption and more isolation compared to bulk silicon circuits.
The ceremony for the 2011 Noble Award took place during the IEEE/MTT-S International Microwave Symposium (MTT 2011) in June 2011 in Baltimore, MD, USA.
This summer, the IEEE also announced the winner of the 2012 Noble award: Subramanian S. Iyer, for “the development and implementation of embedded DRAM technologies.” Dr. Iyer is Distinguished Engineer & Chief Technologist, Semiconductor Research & Development Center, IBM Systems & Technology Group. He wrote about therole of SOI in “eDRAM” technology in ASN6 (December 2006). The technology is now at the heart of IBM’s latest offerings.
Key advances in transistor research start on SOI.
SOI has always been the substrate of choice to explore new silicon device concepts and structures. The full dielectric isolation of the silicon allows one to dismiss the sometimes complex junction isolation schemes used in bulk silicon. The possibility of making devices in thin silicon films has enabled a number of new operation modes such as: volume inversion, where the bulk of the silicon film is inverted; and accumulation-mode operation, in which the channel region has the same doping polarity as the source and drain.
It is only afterwards that bulk processes are devised to mimic the original SOI device: the bulk FinFET is a bulk silicon version of the DELTA device or the SOI FinFET; and the double-gate silicon-on-nothing device is a version of the gate-all-around FET that does not use SOI wafers.
Another key advantage of SOI is the possibility of fully depleting a device. This is obviously not possible in bulk silicon.
Fully depleted MOSFETs have long been known to be “ideal” transistors, featuring optimal subthreshold slope, optimal body effect, better current drive, transconductance and linearity than bulk transistors, and lower soft error rate. They also show lower leakage currents and threshold voltage variation when temperature is increased.
Yet, these devices have not yet been widely adopted by industry. Recent findings by Leti and other research groups show that transistor parameter variability can be reduced when using FD-SOI. This may be the trigger point that may convince the industry.
We can add to the picture the fact that “remote” or “virtual” doping can be achieved using the “back-gate mirror doping” technique, in which forming a doping profile in the substrate below a thin BOX is found to “induce” a similar doping profile in the thin-film SOI device above the BOX. This effect can be used to modulate the virtual doping concentration in channels that are, otherwise, lightly doped or undoped.
But there are also very exciting results at the other side of the doping concentration scale. The recently published junctionless transistor is a heavily doped silicon SOI nanowire pi-gate FET with no junctions nor doping concentration gradients. The doping concentration is as high as what is normally used in source and drain.
Interestingly, the use of very high doping concentrations eliminates the problem of doping fluctuations just as well as the use of undoped channels does. Having no junctions is an obvious advantage when you are considering sub-22nm nodes. It also greatly facilitates the use of semiconductor materials other than silicon.
After having worked on SOI devices for the better part of the last 30 years, I still find it is a fascinating field of research, especially if one considers the advent of quantum effects in nanoscale SOI devices.
 “Back-gate Mirror Doping for Fully Depleted Planar SOI Transistors with Thin Buried Oxide”, R. Yan et al., 2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), April 2010
 “Nanowire transistors without junctions”, J-P Colinge, et al., Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010
Jean-Pierre Colinge brings together work from top researchers in physics, design and fabrication of advanced devices.
Jean-Pierre Colinge has edited a recent addition to Springer’s Integrated Circuits and Systems Series, entitled FinFETs and Other Multi-Gate Transistors. A well-known figure in the SOI world, Colinge brings together chapters contributed by some of the world’s leading experts on multigate FET (MuGFET) technology. In addition to Colinge, contributors include Wade Xiong of TI, Olivier Faynot of CEA-LETI (both of whom also have articles in this current edition of ASN), Chenming Hu of UC Berkeley, and Gerhard Knoblinger of Infineon. Read More