SOI Visionary Sorin Cristoloveanu Receives IEEE 2017 Andrew Grove Award

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ByAdele Hars

SOI Visionary Sorin Cristoloveanu Receives IEEE 2017 Andrew Grove Award

(Courtesy: Grenoble INP)

Sorin Cristoloveanu has been named the 2017 recipient of one of the IEEE’s highest honors, the Andrew Grove Award, for his “contributions to silicon-on-insulator technology and thin body devices.” An IEEE Fellow and highly regarded figure in the SOI community, Sorin is the Director of Research at the French National Center for Scientific Research (CNRS at IMEP-LAHC) in Grenoble, France.  

Here is how the IEEE describes him:

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits.

The Grove Award is given “for outstanding contributions to solid-state devices and technology”. In 2012, it was awarded to another SOI visionary, Jean-Pierre Colinge, “For contributions to silicon-on-insulator devices and technology.”

ByAdele Hars

FD-SOI Training: Over 220 Attend 1st SOI Academy in Shanghai

There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks.

They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we’ll keep you posted (and of course, keep checking back for news on the Consortium’s Events page).

SOI Academy ’18 keynotes by: Dr. Mark Ding, CEO, SITRI; Dr. Carlos Mazure, EVP Soitec and Chairman/Executive Director SOI Consortium. Dr. Julien Arcamone, EVP Leti. (Images courtesy: SITRI). Lower right: the hands-on FD-SOI training.

The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai.

Just to put this in perspective, SIMIT and SITRI are absolutely key players in China’s chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world’s earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China.

At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu.

The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman & Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.”

Day 1: Intro to FD-SOI

The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries.

After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology.

The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored.

Day 2: Hands-on Training

The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers.

Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI.

“The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.”

“The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design & Technologies.

“The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design & Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.”

The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed.

“As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”

ByAdele Hars

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.


Leti: Adding Strain to FD-SOI for 20nm and Beyond

Work at Leti shows that strain is an effective booster for high-performance at future nodes.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Stressor options for FD-SOI technology

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Efficiency of stressor techniques for N & PMOS

Figure 2: Efficiency of stressor techniques for N & PMOS


In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at

– – – – –


[1] C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu,

T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

[2] S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator

(sSOI)”, Solid State Electronics, 2010.

[3] F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI

and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.

[4] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-

On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.

[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,

A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with

HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.

ByGianni PRATA

IEEE SOI Conference

October 2008, New Paltz, NY, USA

Researchers from the world over gathered at the beautiful Mohonk Mountain House in upstate New York this fall to listen to over 50 excellent presentations. Hot topics included memory, reliability and optimization. A selection of some of the best follows below, with links embedded for easy access to the abstracts.


• 7.3: Capping-Metal Gate Integration Technology for multiple-VT CMOS in MuGFETs

A. Veloso, L. Witters, M. Demand, I. Ferain1, N. J. Son, B. Kaczer, Ph. J. Roussel, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer, S.Biesemans, M. Jurczak (IMEC, Samsung, K. U. Leuven)

MuGFETs with caps sandwiched in-between 2 metals (TiN or TaN) in the gate stack were studied for multiple-VTs CMOS applications, resulting in additional understanding on the caps diffusion mechanism, reliability behavior and integration implications. This addresses concerns with regard to the tuning options for narrow fins. It is compatible with 3D device architectures and suitable for high-density circuits at sub-32nm nodes.


• P6.1: Sub-45nm Fully-Depleted SOI CMOS Subthreshold Logic for Ultra-Low Power Applications

D. Bol, R. Ambroise, D. Flandre , J.-D. Legat (U. Catholique de Louvain)

The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional Vdd and static energy. This makes FD SOI with metal gate a strong candidate for sub-45nm robust and energy-efficient subthreshold circuits.

• 1.1: Variability and power management in sub-100nm SOI technology for reliable high performance systems

Das, Koushik; Bernstein, Kerry; Burns, Jeff; Gebara, Fadi; Shih-Hsien Lo,; Nowka, Kevin; Rao, Rahul; Rosenfield, Michael (IBM)

Going forward, variability and power management are very big and inter-related issues. This paper gives an overview of the power/variability challenges in sub-100nm CMOS. It illustrates several circuit, EDA and system level reliability techniques for building robust low-power systems. Finally, to optimally design extremely dense, multi-core chips with billions of transistors, the authors emphasize the need for an approach integrating technology development, VLSI design, design automation tools and micro-architecture.

• 1.2: SOI-enabled MEMS processes lead to novel mechanical, optical, and atomic physics devices

Herrera, G. V.; Bauer, Todd; Blain, M. G.; Dodd, P. E.; Dondero, R.; Garcia, E. J.; Galambos, P. C.; Hetherington, D. L.; Hudgens, J. J.; McCormick, F. B.; Nielson, G. N.; Nordquist, C. D.; Okandan, M.; Olsson, R. H.; Ortiz, K.; Platzbecker, M. R.; Resnick, P.J.; Shul, R. J.; Shaw, M. J.; Sullivan, C. T.; Watts, M. R. (Sandia)

Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers in the mid-1990s to develop a radiation-hardened semiconductor process for sub-0.5μm geometries. The expertise they developed opened opportunities to improve other technologies. This paper presents a high-level description of their SOI process technologies that have enabled a novel devices and products, including an accelerometer, RF MEMS microresonators and contacting switches, integrated optics (low-loss Si waveguides, the smallest and lowest power micro-ring modulators and thermo-optic phase modulators/switches), and ion traps for quantum computing (along with other atomic physics device examples).

• 2.1: Will SOI have a life for the low-power market?

Cai, Jin; Ren, Zhibin; Majumdar, Amlan; Ning, Tak H.; Yin, Haizhou; Park, Dae-Gyu; Haensch, Wilfried E. (IBM)

This paper looks at the key challenges for SOI CMOS to achieve sub-100pA/µm leakage current, which is required for low-standby power applications. Recent 45nm data illustrates the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, the authors identify several unique SOI opportunities that can broaden its appeal to the low power market.

• 3.1: Floating Body Cell Memory for 16-nm Technology with Low Variation on Thin Silicon and 10-nm BOX

U. E. Avci, I. Ban, D. L. Kencke, and P.L.D. Chang (Intel)

The authors demonstrate a scaled planar FBC technology with undoped-body featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. They predict this FBC scaling will be feasible at the 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

• P7.2: Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

Makosiej, Adam; Nasalski, Piotr; Giraud, Bastien; Vladimirescu, Andrei;Amara, Amara (Technical U. Lodz, ISE Paris, UC Berkeley, Leti)

This paper describes two novel sub-32nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10–15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.

• 5.1: High Speed Photonics on an SOI platform

J. Basak, L. Liao, A. Liu, Y. Chetrit, H. Nguyen, D. Rubin, and M. Paniccia (Intel, Numonyx)

This paper talks about the developments in silicon photonic devices that exploit the inherent high refractive index contrasts achievable on an SOI platform. It focuses on the optical modulator that has been designed for speeds up to 40Gbps. It also describes the design and performance of a photonic integrated transmitter chip, which has been demonstrated to transmit at an aggregate data rate of 200Gbps.

• 5.6: A 10-Bit Current-Steering FinFET D/A Converter

M. Fulde, F. Kuttner, K. v. Arnim, B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, M. Becherer, D. Schmitt-Landsiedel, G. Knoblinger (Infineon, Technical U. Munich, IMEC)

The integration of A/D and D/A converters is very important for SoC applications. The authors present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current-steering D/A converter are shown. The achieved performance proves the ability of recent FinFET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching and analog behavior of FinFETs enables reduced circuit area compared to planar designs.

• 6.2: SOI-GeOI hybrid substrates elaboration by Ge condensation: Process and electrical properties

Nguyen, Q.T.; Damlencourt, J.F.; Vincent, B.; Loup, V.; Le Cunff, Y.; Gentil, P.; Cristoloveanu, S. (IMEP-INP, CEA-Leti)

The authors report on the successful fabrication of hybrid SOI-GeOI wafers. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole-mobility in Ge islands and high electron-mobility in Si islands. The data confirms that hybrid wafers are attractive for co-integrating pMOSFETs in Ge and nMOSFETs in Si.

• 6.5: Characterization of a Three-Dimensional SOI Integrated-Circuit Technology

C.K. Chen, N. Checka, B.M. Tyrrell, C.L. Chen, P.W. Wyatt, D.R.W. Yost, J.M. Knecht, J.T. Kedzierski, C.L. Keast; (Lincoln Labs, MIT)

Lincoln Labs established a 3D IC technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. 3DIC technology in the most recently completed run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers. This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determining the impact of 3D vias on ring oscillator performance, and demonstrating functionality of single and multi-tier circuits of varying complexity. The work was sponsored under a DARPA/Air Force contract.

• 7.2: Twin Silicon Nanowire FET (TSNWFET) On SOI With 8 nm Silicon Nanowires and 25 nm Surrounding TiN Gate

D.-W. Kim, M. Li, K. Hwan Yeo, Y. Y. Yeoh, S. D. Suk, K. H. Cho, K. Oh, W.-S. Lee (Samsung)

This paper reports fabrication of twin silicon nanowire FETs on SOI with down to 25-nm TiN surrounding the gate and 8-nm silicon nanowires with high manufacturability. Improved device reliability includes the reduction of junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. High performance is also obtained: 1124μA/μm and 1468μA/μm at off current of 1nA/μm for NMOS and PMOS, respectively.

• 7.5: Optimizing FinFET geometry and parasitics for RF applications

Kranti, Abhinav; Raskin, Jean-Pierre; Armstrong, G. Alastair (Queen’s U. Belfast, U. Catholique de Louvain)

This paper gives a detailed analysis on the impact of parasitic capacitances/resistances and fin geometry in FinFETs for RF applications. RF FinFETs should be designed with Tfin/Lg of 0.6 and AR of 3, along with minimal fin spacing of 50 nm to achieve higher ƒT and ƒMAX values. Although FinFET will always exhibit higher parasitics than an equivalent planar technology, reduction of RSD to ITRS target specification, together with a minimal fin spacing Sfin, results in significant improvement in RF figures of merit.

• 8.1: Scaling and soft errors: Moore of the same for SOI?

Alles, M. L.; Ball, D. R.; Massengill, L.W.; Schrimpf, R. D.; Reed, R. A.;Bhuva, B. L. (Vanderbilt U.)

The continued path on Moore’s Law has increased the concern about soft errors, even in terrestrial applications. Multiple device (multiple bit) interactions and upsets are now one of the major challenges of analysis and mitigation in bulk CMOS devices. This is perhaps the major advantage for SOI with respect to single event effects. New SOI devices, including the MugFETS and ZRAMs, present opportunities for additional detailed study of single event effects as the devices approach the mainstream. One of the interesting aspects of the ZRAM is the difference in data state vulnerabilities compared to the conventional bulk DRAMs. This paper examines single-event effects and implications for SOI CMOS.

• 8.3: Novel SOI-Specific Circuit Form High-Speed Radiation-Hardened Memories

T.P. Haraszti1, R. Pancholy, J. Choma, R. Schober, K. Hunt; (Microcirc, USC, NanoPower, USAF Research Lab)

In all of the seven main memory components, the use of the novel SOI-specific sense amplifiers, memory-cells, and logic gates, evinced exceptionally speedy operations. This made possible fabrication and tests of complete memories which feature 2.2 GHz operational speed, 10−l2 error/bit/day and 1 Mrad total dose hardness. The SOI memories can indeed provide substantially faster operations than their best bulk counterparts do.

• 8.5: Double Thick Copper BEOL in Advanced HR SOI RF CMOS Technology: Integration of High Performance Inductors for RF Front End Module

C. Pastore, F. Gianesello, D. Gloria1, E. Serret, P. Bouillon, B. Rauber, Ph. Benech (STMicroelectronics, IMEP/LAHC)

High-performance on-chip inductors are key RF passive components for most RF circuits. This paper reports on a state-of-the-art inductor integrated in an advanced high resistivity (HR) SOI RF CMOS technology, using a double 3-μm thick back-end-of-the-line (BEOL) module. The inductor performance is comparable to those obtained in dedicated passive component technologies (Integrated Passive Device (IPD) on glass or RF substrates): a quality factor Q greater than 30 and current capability up to 57 mA/μm @ 125 °C. The results pave the way to the integration of the whole RF front-end module (which is currently served by GaAs technologies) in an advanced HR SOI CMOS technology.

• 8.6: High temperature RF behavior of SOI MOSFETs for low-power low-voltage applications

Emam, M.; Vanhoenacker-Janvier, D.; Anil, K.; Ida, J.; Raskin, J.-P. (U. Catholique Louvain, Oki Electric)

At Zero-Temperature-Coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for Low-Power Low-Voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and Partially Depleted SOI MOSFETs with and without body contact are analyzed.

• 9.2: Impact of surface and buried interface passivation on ultrathin SOI electrical properties

G. Hamaide, F. Allibert, S. Cristoloveanu (Soitec, IMEP-INPG MINATEC)

The thickness dependence of mobility in state-of-the-art SOI wafers is essentially an artefact due to the vertical field, stemming from surface charges and increasing as the film gets thinner. Various passivation treatments were used and combined; their impact on top surface and buried interface quality was studied separately. Excellent mobility values, above 650 cm2V−1s−1 for electrons and 200 cm2V−1s−1 for holes were achieved after FGA.

• 9.3: High-k/metal Gate GeOI pMOSFET: Validation of the Lim&Fossum Model for Interface Trap Density Extraction

K. Romanjek, C. Le Royer, A. Pouydebasque, E. Augendre, M. Vinet, C. Tabone, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, L. Clavelier, X. Garros, G. Reimbold, N. Daval, F. Boulanger, S. Deleonibus; (CEA-LETI/MINATEC, Soitec).

The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of Germanium-On-Insulator pMOSFETs is shown using the Lim&Fossum model historically developed for fully depleted SOI devices. This method can be used as a simple and efficient way to monitor the influence of the process on top and bottom interface trap densities and can be used as a process optimization qualifier for GeOI devices.

• 10.1: Ultra-scaled Z-RAM cell

S. Okhonin, M. Nagoga, C.-W. Lee, J.-P. Colinge, A. Afzalian, R. Yan, N. Dehdashti Akhavan, W. Xiong, V. Sverdlov, S. Selberherr, C. Mazure (Innovative Silicon, Tyndall National Institute, Texas Instrument Inc., TU Vienna, Soitec)

Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.

ByGianni PRATA

Conference Proceedings

• Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology
Fabrice Letertre, in Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates, edited by A. Dadgar, T. Li, M. Mastro, E.L. Piner, and J. Redwing (Mater. Res. Soc. Symp. Proc. Volume 1068, Warrendale, PA, 2008).

• Direct Growth of III-V Devices on Silicon
Katherine Herrick, Thomas Kazior, Amy Liu, Dmitri I. Loubychev, Joel M. Fastenau, Miguel Urteaga, Eugene A. Fitzgerald, Mayank T. Bulsara, David Clark, Berinder Brar, Wonill Ha, Joshua Bergman, Nicolas Daval, and Jeffrey LaRoche, in Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates, edited by A. Dadgar, T. Li, M. Mastro, E.L. Piner, and J. Redwing (Mater. Res. Soc. Symp. Proc. Volume 1068, Warrendale, PA, 2008).

• Layer Transfer with Implant-Induced Defects: A Path to Advanced Engineered Substrates
K. K. Bourdelle, Proceedings 17th Intern. Conf. on Ion Implantation Technology, Monterey, CA, June 8-13, 2008.

• Evolution of end-of-range defects in silicon-on-insulator substrates
P. F. Fazzini, F. Cristiano, C. Dupré, S. Paul, T. Ernst, H. Kheyrandish, K. K. Bourdelle, and W. Lerch, Proceedings Spring EMRS 2008 meeting (Symp. I), Materials Science and Engineering B.

• Novel trends in SOI: UTBOX SOI and direct silicon bonding technologies
Oleg Kononchuk and Frederic Allibert, Proceedings of 5th International Symposium on Advanced Science and Processing of Silicon Materials, (Kona, Hawaii Nov. 14, 2008).

• Fundamentals of Wafer Bonding for SOI: From Physical Mechanisms Towards Advanced Modeling
Ionut Radu, Alice Boussagol, Alexandre Barthelemy and Sebastien Vincent, ECS Transactions, Volume 16, Issue 8 pp. 349-360 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

• Weakening of Hardness and Modulus of the Si Lattice by Hydrogen Implantation for Layer Transfer in Wafer Bonding Technology
Diefeng Gu, Helmut Baumgart, Konstantin. K. Bourdelle, George Celler, and A. A. Elmustafa, ECS Transactions, Volume 16, Issue 8, pp. 385-391 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

• Strain Relaxation in Patterned Strained Si-on-Insulator (sSOI) by Raman Spectroscopy
Diefeng Gu, Helmut Baumgart, Mingyao Zhu, George Celler, ECS Transactions, Volume 16, Issue 8, pp. 329-335 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

• Tuning the electrostatic properties of Silicon-on-Insulating Multilayer (SOIM) Structures
M. Kostrzewa, T. Q. Nguyen, J.-P. Mazellier, Ch.Deguet, L. Clavelier, K. Landry, S. Cristoloveanu, Volume 16, Issue 8, pp. 187-194 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

• Engineering Substrates for 3D Integration of III-V and CMOS
K.J. Herrick, T. E. Kazior, J. Laroche, A. W. K. Liu, D. Lubyshev, J. M. Fastenau, M. Urteaga, W. Ha, J. Bergman, B. Brar, M. T. Bulsara, E. A. Fitzgerald, D. Clark, D. Smith, R.F. Thompson, N. Daval, G. K. Celler, ECS Transactions, Volume 16, Issue 8, pp. 227-234 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

• Monolithic III-V/Si Integration
E. A. Fitzgerald, M. T. Bulsara, Y.Bai, C. Cheng, W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. Urteaga, W. Ha, J. Bergman, B. Brar, C. Drazek, N. Daval, F. Letertre, W. E. Hoke, J. R. LaRoche, K. J. Herrick, and T. E. Kazior, ECS Transactions, Volume 16, Issue 10, pp. 1015-1020 (2008) – 214th ECS Meeting, October 12 – October 17, 2008, Honolulu, HI.

ByGianni PRATA

Other papers

• Impact of the transient formation of molecular hydrogen on the microcrack nucleation and evolution in H-implanted Si (001)
S. Personnic, K. K. Bourdelle, F. Letertre, A. Tauzin, N. Cherkashin, A. Claverie, R. Fortunier and H. Klocker, J. Appl. Phys. 103, 023508 (Jan. 2008).

• Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes
Hao-Chih Yuan, Michelle M. Kelly (Roberts), Donald E. Savage, Max G. Lagally, George K. Celler, and Zhenqiang Ma, IEEE Transactions on Electron Devices, Vol. 55, No. 3, March 2008.

• Germanium oxynitride (GeOxNy) as a back interface passivation layer for Germanium-on-insulator substrates
T. Signamarcheix, F. Allibert, F. Letertre, T. Chevolleau, L. Sanchez, E. Augendre, C. Deguet, H. Moriceau, L. Clavelier, and F. Rieutord, Appl. Phys. Lett. 93, 022109 (July 2008), DOI:10.1063/1.296034

• High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding
O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher, N. Daval, D. Lafond, L. Tosti, L. Brevard, O. Rozeau, C. Fenouillet-Beranger, M. Marin, F. Boeuf, D. Delprat, K. Bourdelle, B.-Y. Nguyen, and S. Deleonibus, IEDM 2008.

• Characterization of Pinhole in Patterned Oxide Buried in Bonded Silicon-on-Insulator Wafers by Near-Infrared Scattering Topography and Transmission Microscopy
Xing Wu, Junichi Uchikoshi, Takaaki Hirokane, Ryuta Yamada, Akihiro Takeuchi, Kenta Arima, and Mizuho Morita (Osaka University, Xi’an Jiaotong University) J. Electrochem. Soc., Volume 155, Issue 11, pp. H864-H868 (2008). Revised 17 July 2008; published 9 September 2008.

• Novel Silicon-Carbon (Si:C) Schottky Barrier Enhancement Layer for Dark-Current Suppression in Ge-on-SOI MSM Photodetectors
Kah-Wee Ang, Shi-Yang Zhu, Jian Wang, Khai-Tze Chua, Ming-Bin Yu, Guo-Qiang Lo, Dim-Lee Kwong (Inst. of Microelectron, A*STAR, Singapore) Electron Device Letters, IEEE Publication Date: July 2008 Volume: 29, Issue: 7 page(s): 704-707.

• A Capacitorless 1T-DRAM on SOI Based on Dynamic Coupling and Double-Gate Operation
Bawedin, M.; Cristoloveanu, S.; Flandre, D. (U. Cambridge, IMEP-INP, U. Catholique de Louvain) July 2008, Volume: 29, Issue: 7.

• Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs
Bedell, S.W., Majumdar, A., Ott, J.A. Arnold, J., Fogel, K., Koester, S.J, Sadana, D.K. (IBM), Electron Device Letters, IEEE July 2008, Volume: 29, Issue: 7.

• Very High Efficiency 13.56 MHz RFID Input Stage Voltage Multipliers Based On Ultra Low Power MOS Diodes
Gosset, G.; Rue, B.; Flandre, D. (U. Catholique de Louvain), 2008 IEEE International RFID Conference on 16-17 April 2008.

• ULPFA: a new efficient design of a power aware full adder
Hassoune, I.I.; Flandre, D.D.; O’Connor, I.I.; Legat, J.J. -D. (U. Catholique de Louvain). Circuits and Systems I: Regular Papers, Circuits and Systems I: Regular Papers, IEEE Transactions on [Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on]Volume PP, Issue 99, Page(s):1 – 1.

• Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors
Anuj Madan, Ganesh Samudra, and Yee-Chia Yeo (Georgia Tech, U. Singapore) J. Appl. Phys. 104, 084505 (2008); DOI:10.1063/1.3000481, 24 October 2008.

• Light emission and enhanced nonlinearity in nanophotonic waveguide circuits by III–V/silicon-on-insulator heterogeneous integration
G. Roelkens, L. Liu, D. Van Thourhout, R. Baets, R. Nötzel, F. Raineri, I. Sagnes, G. Beaudoin, and R. Raj (Ghent U.-IMEC, TU Eindhoven, CNRS). J. Appl. Phys. 104, 033117 (2008); DOI:10.1063/1.2967832, 15 August 2008.

ByGianni PRATA

Books & Journals

SOI Materials and Devices, S. Cristoloveanu and G. K. Celler, Chapter 4 of Handbook of Semiconductor Manufacturing Technology, 2nd edition, edited by R. Doering and Y. Nishi (CRC Press, Taylor and Francis Group, Boca Raton, Fl, 2007), pages 4-1 to 4-52

Low temperature diffusion of impurities in hydrogen implanted silicon, S. Personnic, K. K. Bourdelle, and F. Letertre, A. Tauzin and F. Laugier, R. Fortunier and H. Klocker, J. Appl. Phys. 101, 083529 (April 2007). (Soitec, CEA-LETI)

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate, Hao-Chih Yuan, George K. Celler, and Zhenqiang Ma ,IEEE Electron Device Letters, 28 (7), pp. 590-592  (July 2007). (U.Wisconsin-Madison, Soitec)

Study of HCl and Secco Defect Etching for Characterization of Thick sSOI, A. Abbadie, S. W. Bedell, J. M. Hartmann, D. K. Sadana, F. Brunier, C. Figuet, and I. Cayrefourcq, J Electrochem Soc. 154 (8), H713-H719 (2007). (Soitec, IBM, LETI)

Comparison of platelet formation in hydrogen and helium-implanted silicon, X. Hebras, P. Nguyen, K. K Bourdelle, F. Letertre, N. Cherkashin, and A.Claverie, Nuclear Inst. and Methods in Physics Research B, 262,  pp. 24-28 (Aug. 2007).  (Soitec, CEMES/CNRS)

Quantitative study of hydrogen-implantation-induced cavities in silicon by grazing incidence small angle x-ray scattering, Luciana Capello, F. Rieutord, A. Tauzin, and F. Mazin, J. Appl. Phys. 102, 026106 (July 2007). (CEA-Grenoble & LETI)

Structure of elastically strain-sharing silicon (110) nanomembranes, A C Opotowsky, S. A. Scott, C. S. Ritz, D. E. Savage, G. K. Celler, and M. G. Lagally, New J. Phys. 9, 270 doi:10.1088/1367-2630/9/8/270 (Aug.2007). (U.Wisconsin-Madison, Soitec)

7.8-GHz flexible thin-film transistors on a low-temperature plastic substrate,  H-C.Yuan, G. K. Celler, Z. Ma, J.Appl. Phys. 102 034501 (Aug. 2007). (U.Wisconsin-Madison, Soitec)

Effects of high-temperature anneals and 60Co gamma-ray irradiation on strained silicon on insulator, K. Park, M. Canonico, G. K. Celler, M. Seacrist, J.Chan, J. Gelpey, K. E. Holbert, S. Nakagawa and M. Tajima, and D. K. Schroder. J. Appl. Phys. 102, 074507 (Oct. 2007). (Arizona State U., Freescale, Soitec, MEMC, Mattson, JAXA)

ByGianni PRATA

Conference Proceedings

International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
(April 2007):

Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI), Che-Hua Hsu, Weize Xiong, Chien-Ting Lin, Yao-Tsung Huang, Mike Ma1, C.R Cleavelin, Paul Patruno, Mark Kennard, Ian Cayrefourcq, Kyoungsub Shin, Tsu-Jae King Liu (UMC, Texas Instruments, Soitec, UC Berkeley), pp. 174-175.

Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies.  K. Schruefer, K. von Arnim, C. Pacha, J. Berthold, C. R. Cleavelin, T.Schulz, W. Xiong, and P. Patruno(Infineon Technologies, Texas Instruments, ATDF, Soitec)

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL, Collaert, R. Rooyackers, G. Dilliwaya, V. Iyengar, E. Augendre, F. Leys, I. Cayrefourq, B. Ghyselen, R. Loo, M. Jurczak and S. Biesemans (IMEC, University of Surrey, K.U. Leuven, ESAT-INSYS, University of North Carolina at Charlotte, Soitec)  , pp. 176-177.

ECS, Silicon-on-Insulator Technology and Devices 13, ECS Transactions, Volume 6, Issue 4, 2007 (Editors: G. Celler, S. Bedell, S. Cristoloveanu, F. Gamiz, B.Nguyen, Y. Omura):

Embedding Device Solutions in Engineered Substrates, Carlos Mazuré (Soitec), DOI: 10.1149/1.2728835.

SOI Metrology and Characterization in Modern Wafer Production, Oleg Kononchuk, F. Brunier, and M. Kennard (Soitec).  DOI: 10.1149/1.2728865.

Evaluation of different etching techniques in order to reveal dislocations in thick Ge layers, A. Abbadie, J.M. Hartmann, C. Deguet, L. Sanchez, F. Brunier, and F. Letertre (Soitec, CEA-LETI).

A Chromium-free Defect Etching Solution for Application on SOI, J. Mähliß, A. Abbadie and B. O. Kolbesen (JWG University, Soitec).

Complementary Single-Crystal Silicon TFTs on Plastic, H.-C. Yuan, Z. Ma, C. S. Ritz, D. E. Savage, M. G. Lagally, and G. K. Celler (U.Wisconsin, Soitec).

Instability of Threshold Voltage of Flexible Single-Crystal Si TFTs, H. Pang, H.-C. Yuan, M. G. Lagally, G. K. Celler (U.Wisconsin, Soitec).

Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications, Weize W. Xiong, C. Rinn Cleavelin, Che-Hua Hsu and Mike Ma, Klaus Schruefer, Klaus Von Arnim, Thomas Schulz, Ian Cayrefourcq, Carlos Mazure, Paul Patruno, Mark Kennard, Kyoungsub Shin, Sun Xin, and Tsu-Jae King Liu, Karim Cherkaoui, and J.P. Colinge (Texas Instruments, UMC, Infineon, Soitec, UC Davis, Tyndall National Institute).

VLSI Symposium, June 11-14, 2007, Kyoto,Japan

Fully Integrated VLSI CMOS and Photonics, (Plenary talk by C.Gunn, Luxtera)
The future direction of photonics, on SOI and integrated into CMOS circuits. As an example, a 40 Gbps transceiver is demonstrated.

SOI SRAM by ABC-technology for 32nm, (Y.Hirano, Renesas)
The active-body-biased (ABC) structure, where the body-bias is controlled through well-contact is applied to the SRAM cell. It was shown that ABC enhanced the static-noise-margin (SNM) by 27% for 32nm node, and 49% for 22nm node.

Multiple Stress Memorization in Advanced SOI CMOS Technologies, (A.Wei, AMD)
A new stress memorization technique (SMT)featuring source/drain amorphization plus low temperature was presented. It has the additive effect to the conventional high-temperature RTA-induced SMT in terms of drain current enhancement. It was ascribed to the stress localization to the source/drain regions, as a result of amorphization implantation.

Scalability of Direct Si Bonding (DSB) for 32nm node, (H.Yin, IBM)
Defect elimination at STI boundary is discussed with optimization of process sequence, (110) Si thickness, and 45-degree rotated (100) substrate. It is concluded that it is scalable down to 22nm with these countermeasures.

IEEE International SOI Conference (October 1-4, 2007, Indian CA,USA)

BEST PAPER AWARD:  High performance, highly reliable FD/SOI I/O MOSFETS in contemporary high-performance PD/SOI CMOS, V.P. Trivedi et al (ASTS, TSO, Freescale).

45nm SOI and beyond – getting to a general purpose technology, Subramanian Iyer (IBM plenary).

SOI based technology for smart power applications, P. Wessels (NXP plenary).

Analog and RF SOI circuits for low poer or harsh environment applications, L. Demeus (CISSOID plenary).

65nm CMOS Bulk to SOI comparison, J.L. Pelloie et al (ARM, UMC).

Integrated Inductors in HR SOI CMOS technologies:  on the economic advantage of SOI technologies for the inegration of RF applications, F.Gianesello et al (STMicroelectronics, CEA-LETI).

Linear cellular antenna switch for hightly-integrated SOI front-end, T. McKay et al (RFMD).

Physical IP for SOI design infrastructure, JL Pelloie (ARM, invited).

A Plasma Damage Mitigation Concept for SOI Technologies: Lightning Rods, M.Pelella et al (AMD).

Dual Silicide SOI CMOS Integration with Low-Resistance PtSI PMOS Contacts, S. Zollner et al (Freescale).

A Novel Two-Transistor Floating Body Memory Cell, J. Fossum et al (U.Florida, Freescale).

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET, W. Xiong et al (Texas Instruments, Central R&D, Soitec, Tydall National Institute, UC Davis).

Evaluation of FinFET RF Building Blocks, G. Knoblinger et al (Infineon, Technical U.Munich, IMMS, Texas Instruments, Soitec).

Study of Fin Profiles and MuGFETs built on SOI wafers,  P. Patruno et al (Soitec, CEA-LETI, Texas Instruments, Central R&D, UMC, Tyndall National Institute).

High hole mobility GeOI pMOSFETs with high K/metal gate on Ge condensation wafers, L. Clavelier et al (CEA/LETI-Minatec, STM, IMEP/INPG-Minatec).

Insights Into Gate-Underlap Design in FinFETs for Ultra-Low Voltage Analog Performance, A. Kranti et al (Northern Ireland Semiconducytor Research Centre, School of Electrical and Electronic Engineering).

Technology-Based FOM for High Voltage LDMOSFETs-Proof of Value of SOI in Power ICs, M.M. Iqbal et al(Engineering Dept, Cambridge University).

RF Lopwer NLDMOS Technology Transfer Strategy from 130nm to, the 65nm Node on thin SOI, O. Bon et al (STM, University de Toulouse, CEA-LETI).

Gate Controleed Bipolar Action in Ultrathin Body Dynamic-Threshold SOI MOSFET, Y Omura et al (Kansai University).

65nm CMOS Bulk to SOI comparison, R. Mishra et al (GeorgeMason University, IBM).

Circuit Performance Optimization in Advanced PD-SOI CMOS Development, W.T. Chiang et al (UMC, ARM).

3D Stacked Channels: How series resistances can limit 3D Devices Performance, E. Bernard et al (CEA-LETI, STM, NXP, INLINSA).

Innovative approach to drive floating body Z-RAM embedded momory to 32nm and beyond, D. Fisch et al (Innovative Silicon).

Analysis of Sensing Margin in Silicon-on-ONO (SOONO) Devive for capacitor-less RAM Application, E. J. Yun et al (Samsung).

SOI Devices and RO on Thin Dielectric Membrances for Pressure Sensing Applications, B. Olbrechts et al (Universite Catholique de Louvain, Concordia University).

Flexfet™: Independently-Double-Gated SOI Transistor with Variable Vt and 0.5V Operation Achieving near Ideal Subthreshold Slope, D. Wilson et al (American Semiconductor Inc., Boise State University, Tennessee Tech University).

Multi-Gate SOI MOSFET operations in harsh environments, W.Xiong et al, (TI invited, Central R&D, Infineon, Tyndall, UC Davis, Soitec).

Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs, J. Song et al (UC San Diego, TI, Central R&D,UMC, Soitec).

SiGe and Ge Material, Processing and Devices Vol 3 N°7:

In situ HL etching and selective epitaxial growth of doped Ge for formation of recessed sources drains. J.M. Hartmann et al (CEA-LETI, STMicroelectronics).

Nanoscaled MOSFET transistors on Strained Si, SiGe & Ge layers: some integration and electrical features. T Ernst et al (CEA-LETI/IMEP).

Channel material Innovation for continuing the historical MOSFET Performance Increase. D.A. Antoniadis, A. Khakifirooz, I.Aberg, J.L.Hoyt (MIT).

Note: for more papers from last year’s ECS meeting, see the PaperLinks in ASN6.


AlGaN/GaN HEMTs on Epitaxies Grown on Composite Substrate, V. Hoel, S. Boulay, H. Gerard, V. Raballand, E. Delos, J.C. De Jaeger, M.A.Poisson, C. Brylinski, H. Lahreche, R.Langer, P.Bove (I.E.M.N, U.M.R-C.N.R.S, Alcatel-Thales III-V Lab, Picogiga International).  European Microwave Integrated Circuits Conference 2007 (Formerly GAAS®), Munich, 8-10 October 2007.

Nanomechanical Properties of strained Silicon-on-Insulator (SOI) Films epitaxially grown on
Si1-xGex and Layer Transferred by Wafer Bonding, Nathanael Miller, Kandabara Tapily, Helmut Baumgart, A. A. Elmustafa, George K. Celler and Francois Brunier (Old Dominion University, The Applied Research Center-Jefferson Lab, Newport News, VA, Soitec), MRS Proc. April 2007.

Flexible RF/Microwave Switch-PIN Diodes using Single-Crystal Si-Nanomembranes, H. Yuan, Z. Ma,  G. K.Celler, Proc. IEEE MTT-S  Intern. Microwave Symposium 2007 (Honolulu, Hawaii) paper WEP1B-11. (U.Wisconsin-Madison, Soitec)

A Merged MuGFET and planar SOI Process technology, Andrew Marshall, C. Rinn Cleavelin, Weize Xiong, Christian Pacha, Gerhard Knoblinger, Klaus Von Armin, Thomas Schulz, Klaus Schruefer, Ken Matthews, Wolfgang Molzer, Paul Patruno, Christian Russ.  IEEE International SOC Conference (September 26-28, 2007, Hsinchu, Taiwan).  (TI, Infineon, ATDF, Soitec).


10 Years – Already?

One of the world’s leading SOI experts considers Smart Cut innovations and future potential.

I remember a meeting with a PhD student, over ten years ago. He was supposed to work on SIMOX material: at that time, a perfect topic in a perfect SIMOX group with Michel Bruel, André Auberton and Jean-Michel Lamure around. Oddly, this brilliant student enthusiastically tried to convince me that wafer bonding was a more suitable SOI technology. What I didn’t yet know was that the top SIMOX experts – Michel, André and Jean-Michel – were just then discovering the miracle of Smart Cut technology. By the time the PhD was redesigned and defended, Soitec had introduced Smart Cut technology and UNIBOND™ wafers to the marketplace. Read More