KLA-Tencor says its new WaferSight 2 is the industry’s first enabling wafer suppliers and chipmakers to measure bare wafer flatness, shape, edge roll-off and nanotopography in a single metrology system for 45nm and beyond. SOI wafer-supplier Soitec was a beta site.
The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.
If you don’t have time to look at all of the ppts, here are quick overviews.
Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:
He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.
Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.
Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:
Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).
This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.
In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.
Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.
K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.
SOI technology is at the base of cellular wireless connectivity: 4G and 5G are driving up the demand for both 300mm and 200mm capacity, both in short supply. The 4G expansion and the introduction of 5G are also enlarging the scope to new applications and new frequency ranges, up to supporting mm-wave. The demand is not only about supporting continuously growing volumes, but requires to develop solutions using differentiated silicon technologies (RF-SOI, PD-SOI, FD-SOI) and to offer integrated system solutions (in-package modules, including integrated antennas).
The workshop has develop such requirements and the current solutions available from a supply chain perspective, involving substrate suppliers, equipment and material suppliers (for both substrate/silicon manufacturing and packaging solutions), and foundries.
Enabling the Engineered SOI Wafer, Sesh Ramaswami, Managing Director, Applied Materials (presentation not available)
Synergies with the SOI Industry, Olivier Vatel, Corporate Director, Senior Vice President and CTO of SCREEN Semiconductor Solutions, Screen (presentation not available)
Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH
Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor
Paul Boudre has been named CEO of SOI wafer leader, Soitec (see financial press release here). The company also announced its plans to re-focus on its core electronics business unit.
Q3 sales were 48 million euros, up 45% over last year. The sale of 200mm wafers (which are used in chips for RF-SOI and smartpower) were almost doubled from last year, and now represent three quarters of the company’s wafer sales. 300mm wafers (which are used for partially and fully-depleted SOI logic) were up by 16%. The company expects to see the ramp for 300mm FD-SOI wafers in H2 2015.
Boudre joined Soitec from KLA-Tencor in 2007. He has served as the company’s COO since 2008. He now takes over the CEO role from the company’s founder, André-Jacques Auberton-Hervé, who will continue as Chairman of the Board.
Soitec is restructuring its solar business and implementing cost-cutting measures.
SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently.
Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept – that she made at Semicon West ’11.
(If you need a quick backgrounder on FD-SOI basics, see this explanation from the SOI Industry Consortium.)
Laurent Malier, CEO of Leti – the process technology:
Amir Azordegan, senior director of marketing for Surfscan at KLA-Tencor – the inspection systems:
Paul Lindner, executive technology director, EV Group – wafer bonding systems:
Robert Newcomb, executive VP of operations, Qcept Technologies – advanced defect detection technologies:
At the 45nm node, substrate quality and uniformity are more critical than ever before to ensuring the best possible device performance. This is especially true in SOI wafers, where the substrate’s electronic structure is engineered to play an active role in enhancing carrier mobility or decreasing leakage current.
Semiconductor manufacturers producing SOI-based devices utilize the Surfscan SP2XP as part of a comprehensive yield management strategy. Featuring improvements in sensitivity, production throughput and killer defect classification, the Surfscan SP2XP is used for incoming wafer quality control, process tool monitoring and unpatterned wafer defect inspection. It is designed to help chipmakers accelerate production of their leading-edge, SOI-based devices. Read More
Announcements in worldwide and Asia sales; China distribution.
Soitec, the world’s leading supplier of engineered substrates, has announced key appointments to its sales team and finance department, and a new distribution partnership for markets in China. Read More
With promotion from EVP Sales & Marketing, industry veteran also takes on operations.
Paul Boudre has been appointed Chief Operating Officer (COO) of SOI wafer-leader Soitec.
He first joined joined Soitec’s executive team in January 2007 as a core member of the office of the president, moving into the position of Executive Vice President of Sales, Marketing and Customer Support. Most recently, the R&D organization also moved under his responsibility, to ensure closer alignment and long-term partnership with strategic customers. Read More
New in-line inspection equipment from KT reaches new heights in accuracy for sorting out cleanable particles from killer defects.
At the 45nm node, the very nature of the defects and the particularities of the substrate impact light scattering detection methodologies.
KLA-Tencor’s new Surfscan SP2XP system not only captures more shallow defects like stains or residues, it significantly improves the ability to distinguish cleanable particles from killer defects. Read More
After several years of rigorous R&D work in close partnership with suppliers and customers alike, Soitec’s sSOI wafers are now ready for industrialization.
The benefits of strained silicon as an amplifier of carrier mobility, current drive and, as a result, device performance are well documented in literature and highlighted by Dr. Nguyen of Freescale in this same Advanced Substrate News issue. A strained silicon wafer platform was needed to assure the scalability of process-induced strain from the 45 nm technology node through the 32 nm node and further. Strained Silicon-On-Insulator (sSOI) is the answer.
sSOI is an evolutionary approach to SOI combining the advantages of SOI with the benefits of strained silicon. From the device perspective, it complements the processinduced stressor techniques. The device is engineered bottom-up from the substrate. The tensile strain in the NMOS regions is maximized during subsequent CMOS processing, while in the PMOS regions the tensile strain is first relaxed before introducing a compressive strain component along the channel. sSOI is a strain platform that allows the engineering of the appropriate tensile and compressive stress components along and across the channel independently for both transistor types.
sSOI is now ready to move into the 300 mm industrialization phase, the next ambitious phase of this program. Undoubtly, the development of sSOI has profited from the strong synergy with SOI, helping accelerate the development. But for a product based on the transfer of an epitaxial strained layer, the development of the silicon germanium template for the strained silicon layer growth and of the appropriate metrology became a crucial part.
The development of sSOI and the establishment of a robust industrialization solution have been characterized by the strong partnership between equipment suppliers like ASM, SEZ, KLA-Tencor and OMI and by the strong coupling between device and substrate engineering with companies like Freescale.
At present, the tool set is defined, sampling and monitoring metrology identified and most important: sSOI product wafer is available. The main concern of the IC industry was the crystal quality of sSOI. Today’s sSOI quality has reassured the industry by eliminating killer defects like dislocation pile-ups and strongly reducing the dislocation density as shown in Figure 1. The current quality of this new substrate is compatible with complex IC fabrication.
With 500 wafer starts per month in 300 mm we assure sSOI availability to support device architecture development and continue on the rapid quality improvement of this new technology platform.
sSOI is fully compatible with partially and fully depleted device architectures, and has been proven for FinFETs and Multi Gate FETs. sSOI as a template for subsequent epitaxy opens the door to band gap engineering in combination with Ge or SiGe germaniumrich epitaxy. Also known as “dual channel”, the technique has been shown to lead to the highest hole mobility values achieved for a PMOS. sSOI built-in stress averages 1.4GPa. Its scalability to 2.5GPa has been demonstrated, enabling further performance enhancement (Figure 2).
In summary, sSOI offers the industry a powerful, high-mobility platform today.