Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) – which was just a year after they had announced mass production of 28FDS process technology.
At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology.
Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry’s current and future demands especially in consumer, IoT and automotive applications.
In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”
Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI.
At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety).
Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe’s largest independent IC design consultancy.)
In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows.
For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.
And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP & GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D & 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.
In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.)
This is leading to some really nice wins for NXP. For example, they’ve got Amazon’s Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.
Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”.
As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.
ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.
Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?
Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.
OCEAN12 deals with “Ultra-low power computing solutions for automotive and aeronautics using all the range of FDSOI technologies”. This project with a budget of 103M€ brings together 27 partners from 7 different countries. The project received the ECSEL JU* label under the 2017 call. ECSEL is an EU-driven public-private partnership enabling the co-financing of innovation in electronic components and systems both by Member States and the European Union.
ASN: Why is this project needed?
FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require power consumption equivalent to 50 to 100 computers running continuously (without taking into account the car propulsion).
The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.
The FD-SOI substrates, technologies and designs developed in OCEAN12 offer a palate of different solutions to this challenge: increased performance for data processing (including Artificial Intelligence); much higher energetic efficiency; and smaller form factors to fit in embedded systems like autonomous cars with higher integration and reliability, and enabling safe connectivity.
The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.
ASN: What are the project goals?
FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption in the automotive industry.
As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of integrated circuits up to the system and end-user application levels. We will show that the technology is advantageous for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.
The OCEAN12 project goals stand on three pillars:
First: Confirming the technology foundation. Ocean12 puts the FD-SOI substrate and device developers in direct contact with the full value chain of suppliers and end users. This gives the entire ecosystem visibility into current and future needs, and ensures that substrate and device solutions are both technically feasible and correctly aligned with actual system requirements.
Second: Creating concrete, innovative demonstrators in automotive (Audi, Bosch) and aeronautics (Airbus, Thales). These demonstrators are a first step in defining the context and environment to prove the advantages of these technologies in real application cases, showing they are useful and as such prefigure a final system and a potential future product roadmap. Demonstrators should be as close as possible to the final application.
Third: Broadening the design ecosystem, with the big companies, the small- and medium-sized companies (SMEs) and the research organizations (universities, RTOs). We have a critical mass of 16 design ecosystem partners focusing their efforts on FD-SOI. The project leverages that dynamic FD-SOI design ecosystem for IC product migration to FD-SOI and the creation of new IP. Inventing the future components in Europe is also key.
ASN: Can you tell us more about the demonstrators? When will we see them?
FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:
Always-on wake-up systems (Audi, Bosch, Leti). With such a system we can imagine an application to monitor our car when it is parked in a parking lot for a long time. The sensors would remain aware of everything that goes on around the car. Based on sensor observations, the car can make decisions on further actions to take. This can be used in many future car applications like intrusion detection or vehicle access systems. But you will not have to worry about battery drain: even though all the sensors are always on, they go right back into a very low-power sleep mode thanks to FD-SOI technology.
mm-Wave integrated radar SOCs (Bosch and Audi), which will benefit from all the innovations of FD-SOI thanks to its low consumption properties, but also the optimization of the sensors. The performance gain is made over the entire system with adaptations between analog and logic.
High-performance video processor for aeronautics. (Airbus, Thales, Kalray). Kalray, a French SME working on Massively Parallel Processor Arrays (MPPA) aims to demonstrate an ultra-low power, low-cost, high-performance neural processor on FD-SOI technology. This demonstrator would be key for Airbus and drones with high-performance, low-power cameras. Airbus and Audi have partnered on air and ground mobility services.
Microcontroller plug-and-play board. This demonstrator lead by ST will allow for the development of new solutions in the domain of GNSS/GPS.
ASN: Can you tell us more about the partners?
FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.
The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, as a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.
Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer(GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.
In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design&Reuse.
All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their fields of activity. Their contributions are essential for the success of the project.
ASN: What is the timetable?
FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.
ASN: Can you clarify the funding structure?
FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M.
These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems.
To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.
*ECSEL JU: Electronic Components and Systems for European Leadership Joint Undertaking
2019 will be a busy fall for the SOI Consortium and our members.
First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates & locations locked in, so you’ll want to mark your calendars:
The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany.
The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.
Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website.
You’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration.
Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.
And finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including:
If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below.
IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality.
All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.
Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.
Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.
It’s a great program:
1:00pm – Welcome by Semi
1:10pm – IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP
1:35pm – The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials
2:00pm – The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries
2:25pm – Engineered Substrates – Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec
2:50pm – Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG
3:15pm – Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:
4:05pm – Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium
4:20pm – End
This is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!
And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R&D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.
The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai.
Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums.
The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website — click here to get them.
Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.
Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes.
Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.
Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips.
The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF.
All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.
Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)
At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.
Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.
The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.
We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.
For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.
There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.
SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.
Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.