Category Archive In & Around Our Industry

ByAdele Hars

Synopsys IP for 22FDX Automotive – Why It Matters (Courtesy: D. Nenni, semiwiki)

Daniel Nenni, CEO & Founder, SemiWiki.com

Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.

By Dan Nenni, CEO & Founder, SemiWiki.com

IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.

Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.

(Courtesy: semiwiki.com and GlobalFoundries)

The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.

I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.

I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.

One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.

Mark provided a GF link for more information:

Here is the link to our Automotive resources:
https://www.globalfoundries.com/mark…ons/automotive

One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.

Here is the press release:

Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process

Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs

MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Highlights:

  • Synopsys DesignWare IP for automotive Grade 1 and Grade 2 temperature operation on GLOBALFOUNDRIES 22FDX®process includes Logic Libraries, Embedded Memories, Data Converters, LPDDR4, PCI Express 3.1, USB 2.0/3.1, and MIPI D-PHY IP
  • Synopsys’ IP solutions implement additional automotive-grade design rules for the 22FDX process to meet reliability and 15-year automotive operation requirements
  • Synopsys’ IP that supports AEC-Q100 temperature grades and ISO 26262 ASIL Readiness accelerates SoC reliability and functional safety assessments
  • Join Synopsys and GLOBALFOUNDRIES at Mobile World Congress in Barcelona, Spain on Feb. 25 for a panel on “Intelligent Connectivity for a Data-Driven Future”

Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.

“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”

“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”

“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”

Resources
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:

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About the Author

Daniel  Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”.  He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.

ByAdele Hars

Outstanding 28nm FD-SOI Chips Taped Out Through CMP

ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.

CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.

As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.

Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.

8 (of Many) Great Chips

FD-SOI, said Dr. Cathelin, “…is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in  analog, RF/millimeter wave,  Analog/Mixed-Signal and digital design. If you’re a designer, you’ll want to check those out.

Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP’s MPW services. Here they are. (You can click on the illustrations to see them in full screen.)

1. A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

(Courtesy: CMP, ST, ISEN)

This chip was presented at ESSCIRC ’16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells.

2. 28FD-SOI Distributed Oscillator at 134 GHz and 202GHz

(Courtesy: CMP, ST, ims)

Presented at RFIC ’17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.

3. A 128 kb Single-Bitline 8.4 fJ/bit 90MHz at 0.3V 7T Sense-Amplifier-less SRAM in 28nm FD-SOI

(Courtesy: CMP, ST, Lund U.)

Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC ’16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues’ team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn’t need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.

4. Matched Ultrasound Receiver in 28FDSOI

(Courtesy: CMP, ST, Stanford U.)

Presented at ISSCC ’17 (with an extended relative paper at JSSC ’17) by M-C Chen et al with Professor Boris Murmann’s team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It’s a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “…an emerging medical imaging modality based on optical excitation and acoustic detection.” It’s used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.

5. SleepTalker – 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC

(Courtesy: CMP, ST, UCL)

Presented at VLSI ’16 and JSSC ’17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that’s a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “…threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. […] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”

6. A 128×8 Massive MIMO Precoder-Detector in 28FDSOI

(Courtesy: CMP, ST, Lund U.)

This massive MIMO chip was presented at ISSCC ’17 by a team from Professors Liang Liu and Ove Edforss at the Lund University  in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can’t be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team’s intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”

7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI

(Courtesy: CMP, ST, KU Leuven)

Today’s solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10’s to several 1OO’s of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC ’17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “…the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”

8. Fine-Grained AVS in 28nm FDSOI Processor SoC

(Courtesy: CMP, ST, UC Berkeley)

As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC ’16 and JSSC ’17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “… extremely fine-grained (<1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.)  These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium’s FD-SOI Training Day in Silicon Valley, 27 April 2018 –  click here for sign-up information.)

More SOI Through CMP

At the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST’s SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS & micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).

CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don’t hesitate to inquire, as they’ll be adding more.

For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report.

For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here.  Training kits and tutorials will be available in Q3 of this year.

And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.

So lots of terrific SOI resources for CMP – check it out!

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Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.

ByAdele Hars

FD-SOI in China – Foundries See Interest Mounting Fast

The foundries sent their top guns to the FD-SOI Forums organized by the SOI Consortium and its members in Shanghai and Nanjing. This is a quick recap of what they said.

GF: Winning with SOI

“With FD-SOI, we can deliver a level of integration never before possible,” said GlobalFoundries CEO Sanjay Jah in his Shanghai talk, Winning With SOI. The ecosystem they’re building is covering both design and supply. He showed a video of the new fab, which is going up at an enormous speed in Chengdu, China. It’s huge: a half-kilometer long on one side. And it will start producing wafers in H218, ramping up to a million/year.

GlobalFoundries CEO Sanjay Jah citing key TAMs at the FD-SOI Forum in Shanghai. (Photo courtesy: SOI Consortium & GlobalFoundries)

FD-SOI is past the discovery phase now, he continued. They’ve got 135 engagements and 102 PDKs downloaded. In China alone, they have ten customers taping out 15 products. The key is going after high-growth markets, including mobility, IoT, RF/mmW and automotive (see picture above). “We see intelligence migrating to the edge,” he said.

With 22FDX®, there are 11 fewer mask steps than industry standard 28nm HKMG processes, he said. Back bias is a big differentiator, reaping benefits without penalties and shortening time-to-market. eMRAM is also a big driver of interest. The IP – both foundation and complex – is silicon-proven: you can measure it. The FDXceleratorTM program now has 35 partners.

He also touched on RF-SOI, where GF is #1 in terms of market share.

“I’m very excited about the future for us,” he concluded.

With back bias, you can do even more, said GF’s Sanjay Jha, so customers feel the risk is lower. (Photo courtesy: SOI Consortium & SOI Consortium)

In the Nanjing SOI forum, GF’s head of China sales, Zhi Yong Han gave an excellent presentation that is posted on the SOI Consortium website (you can get it here). He emphasized that they are educating designers to help them take advantage of the FD-SOI for advanced devices, as well and working with universities. The result is that they’re seeing significant growth in the Chinese market.

Slide 9 from GF’s Nanjing presentation shows all the boxes ticked: 22FDX® is qualified for volume production. (Courtesy: GlobalFoundries and the SOI Consortium)

Zhi Yong Han also highlighted the excellent performance of GF’s RF-SOI offering, and the huge capacity they’re building out. NB-IoT clients are now approaching them, he added.

Samsung: World’s 1st eMRAM Test Chip

“E.S. stands for Engineering Sample,” quipped Dr. E.S. Jung, EVP/GM of the foundry business for Samsung Electronics. A very energetic speaker, his talk covered Cutting Edge Technology from a Trusted Foundry. (Samsung Foundry is now a standalone business unit.)

Samsung has seven major 28nm FD-SOI customers, and has taped out over 40 products. This coming year a number of products will be taking off in mass production, he said.

eMRAM (which only required three additional mask steps) is the newest addition to the family of embedded non-volatile memories and it offers unprecedented speed, power and endurance advantages (see the press release here).

Regarding back bias in the IP, he said they’ve solved it working with their suppliers, EDA vendors and customers. Migrations will re-use that IP.

At the Nanjing SOI forum, VP of Samsung Foundry Suk Won Kim looked at design methodology in his talk, 28FDS Samsung Foundry Platform. It’s easy to implement your SoC with FD-SOI technology, he said, explaining how PPA and cost/transistor makes 28FDS an optimal node. The PDK – including RF – are ready for high volume production. There is no design overhead: the differences between FD-SOI and bulk are not difficulties, he emphasized.

For 28FDS, the full spectrum of the ecosystem is available: design enablement, advanced design methodologies, and silicon-proven IP. Samsung has a body bias generator, and the design methodology takes care of checking the body bias integrity. In terms of the physical design, there is awareness in the floorplan for body biasing and flip-well devices. In terms of timing sign-off, there’s almost no change – in fact there are fewer PVT corners. The flow for power integrity sign-off doesn’t change. The RTL-to-GDS flow is about the same – and where they diverge, designers are embracing the differences.

And for those looking ahead, the PDK for 18FDS evaluation will be available soon.

More pics?

For pics of many more slides, check out articles posted about the SOI forums in the China press, including EETimes China, EEFocus, and EDN China (plus see their focus piece).

BTW, there were five days of events in Shanghai and Nanjing, with over 50 presentations  given in ballrooms full-to-bursting. As noted in my previous post, China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth, many (but not all) of the presentations are now available  in the Events section here on the SOI Consortium website.

So in future posts, we’ll cover the EDA/IP companies, design tutorials and user presentations for both the FD-SOI and RF-SOI China events — including those not posted. Stay tuned!

ByAdele Hars

New Advanced NV Memory IP for FDSOI – Attopsemi Joins GF’s FDXcelerator Program

There’s a new memory IP specialist on board for the FDSOI ecosystem. Attopsemi Technology has joined GlobalFoundries’ FDXcelerator™ Partner Program (read the press release here). Attopsemi is ensuring that its scalable, non-volatile one-time programmable (OTP) memory IP is compatible with GF’s 22FDX® technology. Their leading-edge I-fuse™ OTP IP is a fuse-based OTP technology that can guarantee zero-program defect, and offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current compared to traditional e-fuse technologies. This advanced OTP targets customers and designers working on harsh, demanding applications such as automotive, 3D IC, and IoT.

“Attopsemi’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

ByAdele Hars

NXP’s new i.MX 7ULP On 28nm FD-SOI – Yes! Industry’s Lowest Power General Purpose Applications Processor (part 1)

They’re calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It’s NXP’s new i.MX 7ULP general-purpose processor, and it’s on 28nm FD-SOI. They’ve got a nifty video summing it all up – you can watch it here.

NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It’s got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)

With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.

The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.

Hello, IoT!

The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.

With the i.MX 7ULP, NXP’s targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it’s designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)

The details

The i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It’s got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors.

(Courtesy: NXP)

NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.

Leveraging body biasing and more

NXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.

In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages:

  • Large dynamic gate and body biasing voltage range

  • Domain and subsystem optimization with custom standard cell library with mixed voltages

  • Low quiescent current (Iq) bias generators

  • Enhanced ADC performance with unique FD-SOI attributes

  • Fail Safe I/O for simplified low power system design

To that, add a note about security. As the chip’s fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it’s needed.

Samsung fabs, Verisilicon adds IP

Two other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP’s results.

“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”

NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.

“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”

So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.

— By Adele Hars, ASN Editor-in-Chief

ByAdele Hars

Part 2: NXP’s new i.MX 7ULP – More on Why It’s On 28nm FD-SOI

i.MX 7ULP (Courtesy: NXP)

As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.

If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)

To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:

  • Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.

  • Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.

  • Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.

  • Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.

  • Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.

  • RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.

  • Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.

  • Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.

  • Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.

But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”

Next up: i.MX 8 for automotive +

At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.

We’ll cover it in an upcoming ASN blog, so stay tuned!

— By Adele Hars, ASN Editor-in-Chief

ByAdele Hars

SOI Consortium Welcomes ASN News

Changes are afoot on the SOI Consortium website. You’ve seen our great new look. Now we have also brought Advanced Substrate News (known to most as ASN) into our fold.

ASN has been bringing you SOI-related news for over a decade now. Editor-in-Chief Adele Hars will continue leading the charge, working closely with the Consortium’s expanding membership base to bring you key news and fresh perspectives from our industry.

The SOI ecosystem is kicking off a banner year in 2017. For example, we just got the news (read more here) that Consortium member GF is teaming up with Chengdu municipality in China on a new fab offering 22FDX, GF’s 22nm FD-SOI process technology. GF is also expanding Dresden’s capacity by 40 percent and augmenting their Singapore fab’s RF-SOI.

That’s just the tip of the iceberg. Watch these pages for more news from our members and the greater ecosystem (if you’re not yet signed up for our email alerts, please take a moment to fill in the form here). In addition to FD-SOI and RF-SOI, we’ll be further expanding our coverage of other fields leveraging SOI such as MEMS, photonics, power and more.

The Consortium will of course continue offering our extremely successful workshops and training sessions (April in Silicon Valley, June in Tokyo, September in Shanghai plus events in Europe TBA). If you can’t get there yourself, don’t worry. ASN will bring you up-close coverage of these events.

And finally, 2017 marks the 10th anniversary of the founding of the SOI Industry Consortium. We thank you all for your decade of support, and welcome your participation. (If your company is not yet a member, click here to learn more about how to join.)  

The SOI ecosystem is more dynamic than ever. Of course we still have plenty of work to do, and we look forward to sharing Consortium and ecosystem successes (and challenges!) with you here at ASN’s new home. We’d love to hear from you – and if you have an idea for a contributed article, please drop Adele an email.

Many thanks. Here’s to the beginning of a dynamic new partnership between the SOI Industry Consortium and ASN.

With best regards,

Carlos Mazure and Giorgio Cesana

Executive Directors

SOI Industry Consortium

 

ByAdministrator

12nm FD-SOI on the Roadmap for H1/2019 Customer Tape-out! Says GloFo (While Giving 22FDX Ecosys a Great Boost)

gf_logo12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).

gf_12fdxslide16lowres

(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology.  “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”

The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

All About 12

GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.

The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.

gf_12fdxslide20lowres

(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).

22 Design Plug ‘n Play

Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.

Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  • tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  • a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology; and
  • product packaging and test (OSAT) solutions.

Additional FDXcelerator members will be announced in the following months.

By

NXP, Qualcomm, Skyworks to Keynote IoT Theme in Upcoming IEEE SOI-3D-SubVt (S3S) Conference (San Francisco, Oct.’16) – Late News Submissions Open, Advance Program Available

IEEE S3S Conference

10-13 October 2016

Hyatt Regency San Francisco Airport

IEEE SOI3DSubthreshold Microelectronics Technology Unified Conference

Theme: Energy Efficient Technology for the Internet of Things

Late News submissions open and Advance Program available

S3SconflogoThe IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.

This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.

We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.

Our Keynote speakers are decision-makers from major industries:

  • Nick Yu, VP, Qualcomm, will explain why “The Homogeneous architecture is a dead fairy tale”
  • Ron Martino, VP, NXP, will present “Advanced Innovation and Requirements for future Smart, Secure and Connected Applications”
  • Peter Gammel, CTO, Skyworks, will describe “RF front end requirements and roadmaps for the IoT”

Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.

Applications will be illustrated in our session dedicated to SOI circuit implementations.

ieee_logo_mb_taglineYou can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.EDS-Logo-Reflex-Blue-e1435737971222

And you still have time to actively participate by submitting a late news paper before August 31st.

The conference has a long tradition of allying technical and social activities.

This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.

Hyatt Regency San Francisco Airport

Hyatt Regency San Francisco Airport

With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.

Deadline for Late News submissions is

August 31st, 2016

register-now-button

For further information, please visit our website at s3sconference.org or contact the conference manager:

Joyce Lloyd • 6930 De Celis Pl., #36

Van Nuys, CA 91406

T 818.795.3768 • F 818.855.8392 • E manager@s3sconference.org

ByAdele Hars

Why Dan Hutcheson/VLSIresearch, Inc. (finally!) Likes FD-SOI

Dan Hutcheson, CEO of VLSIresearch, Inc. finally likes FD-SOI. That’s important, because he’s a really influential person in the chip world. Everybody who’s anybody in the chip biz pays attention to what VLSIresearch, Inc. has to say.

Dan recently gave a talk entitled “FD-SOI: Disruptive or Just Another Process?” to a packed-to-the-brim room during the FD-SOI Symposium in San Jose. (The ppt he used there is available on the SOI Consortium website – download it for free here).

DanHutchesonVideopicHappily for those who didn’t make it to San Jose, Dan then went into the studio and made a video encore of his presentation for all to see – and it’s now posted on his weSRCH site. So you get not just his slides, but also his explanations and comments.

It’s about 20 minutes long – and worth every second. (Recommendation: open the ppt presentation (link here) and the video (link here) in separate windows so you can follow his slides as he talks.)

But for those of you who just want a quick recap, here are some of his key points.

He Did A Survey

Dan, as he’s always quick to point out, is an economist, albeit one extremely well-versed in chip technology. He always thought SOI was an elegant solution, but didn’t see cost savings in the fab as a driver. When asked to give a talk in San Jose, he decided to brush up a bit on what people were saying about FD-SOI. So he did an informal survey – and of course, being Dan, he can talk to just about anyone he wants.

In this case, he talked to decision makers from about a dozen top companies in the chip biz – enough to give him a 95% confidence level in his results. And the results are impressive: almost ¾ said they had FD-SOI designs underway or had already used it, while only about a third said they’ll stick firmly to bulk.

And Found That It’s About Time-to-Money

It turns out that there are companies out there doing both FinFETs and FD-SOI. Why? They’ve figured out the differentiable features, they told him. And some designers are now saying that FD-SOI is actually easier to design in than FinFETs, with one company reporting that design time in FD-SOI was half that of FinFETs.

Dan learned that the two biggest drivers of FD-SOI are IoT and automotive – IoT because those super power-stingy chips get enormous leverage out of back biasing, and automotive for reliability (and for both they get ease of analog integration).

VLSIResearch_FDSOI_markets_SJslide16

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

But at the heart of it, it’s a business case: “It’s not about cost,” he says. “It’s about time-to-money.” With FD-SOI, TTM is significantly faster.

VLSIresearch_FDSOI_bizcase_SJ2016

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

Those that go with FinFET are more often a big company (so they can afford the high NRE* costs) with a huge market, big die and a lot of digital. But if the market’s smaller, faster-moving and needs scaled-down NRE costs, then the people Dan talked to said they are turning to FD-SOI. They see it getting them to market faster, gives them lots of “knobs” and advantages in terms of power, reliability and analog integration, it’s easier to design in, and really enables product differentiation. In fact Dan had analog folks telling him that FD-SOI gave them back some of their favorite tricks and tools that they’d lost after the 130nm node.

(Courtesy: VLSIresearch and SOI Consortium)

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

Finally, Dan sees FD-SOI as a technology with both a long history and a long lifetime ahead. FD-SOI is not in itself disruptive, but is rather an enabler of disruption. The disruption, he says, is IoT. By all means check out his video if you want more detail on his perspective on IoT, automotive and the foundry offerings.

 In conclusion, he urges users to strengthen the ecosystem’s momentum by disclosing their success stories – though he also sees how they might be reluctant to, as FD-SOI is the secret sauce that gives them a huge competitive advantage. But in the end rewards will be reaped, as driving volume up will drive costs down.

If you have a good FD-SOI design story you’d like to share, let us know here at ASN – we’ll be happy to consider it for publication, to help get the word around.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).