Category Archive Industry Buzz

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.

New Bluetooth 5 RF IP from VeriSilicon Targets Wearables, IoT on GF’s 22FDX

Since about a third of all IoT devices are expected to be connected by Bluetooth, chip designers need IP solutions that will help reduce system cost and greatly improve battery life. And that’s just what VeriSilicon has announced for GlobalFoundries’ 22FDX® (FD-SOI) process.

“By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs,” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. 22FDX enables efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. GF and VeriSilicon are working on an SoC using VeriSilicon’s BLE 5.0 RF IP in GF’s 22FDX process.

The latest iteration of Bluetooth is 5, which (like its predecessor 4) has a Low Energy (LE) RF option – but with big improvements. According to the Bluetooth website, “With 4x range, 2x speed and 8x broadcasting message capacity, the enhancements of Bluetooth 5 focus on increasing the functionality of Bluetooth for the IoT.” BLE 5.0 was designed for very low power operation and is optimized for the sorts of short burst data transmissions you’ll get with IoT.

On the strength of VeriSilicon’s innovative RF architecture and by leveraging GF’s 22FDX technology, VeriSilicon says the new IP product achieves significant improvements in power, area, and cost compared to current offerings, so it will better serve the emerging and increasing wearable devices and IoT applications space.

“VeriSilicon’s BLE IP complements GF’s 22FDX FD-SOI capabilities and is well positioned to support the explosive growth of low-power IoT and connected devices,” said Mark Ireland, vice president of ecosystem partnerships at GF. “Together, we broaden our IP and services to further enable our mutual clients to provide power and cost efficient solutions.”

VeriSilicon BLE 5.0 RF IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management.

You can read the full press release in Chinese here and in English here.

QuickLogic ultra-low power eFPGA on GF’s 22FDX FD-SOI and in PULP/RISC-V SoC

(Courtesy: PRNewsfoto/QuickLogic Corporation)

Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now.

ArcticPro is the industry’s first eFPGA offering for GF’s 22FDX® process (btw they’ve been shipping it in volume for GF’s 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device’s functionality in the field.

(Image courtesy: QuickLogic)

QuickLogic has also announced that the technical university ETH Zurich  will integrate QuickLogic’s ArcticPro technology onto the university’s PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF’s 22FDX process node. They will develop an SoC integrating ETHZ’s open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption.

“The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” said QuickLogic CTO Dr. Timothy Saxe. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”

ETH’s PULP platform with the fully integrated eFPGA is expected to be available Q1′ 2019.

QuickLogic is part of GF’s fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.

pSemi: World’s First Monolithic SOI Wi-Fi FEM

pSemi (formerly Peregrine, now a Murata company) has staked its claim for having the world’s first monolithic SOI Wi-Fi front-end module (FEM)—the PE561221. This 2.4 GHz Wi-Fi FEM is the first to integrate a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T) on a single SOI CMOS die. pSemi says it’s ideal for Wi-Fi home gateways, routers and set-top boxes (read the full press release here).

Driving this is the new WiFi standard, IEEE 802.11ax, which launches next year. While it’s largely meant to tackle issues with WiFi in crowded places, it’s also going to be welcome in high-demand home situations. (There’s a good piece on the NetworkWorld site on what 802.11ax will do compared to the current 802.11ac – you can read it here).

The PE561221 uses a smart bias circuit to deliver a high linearity signal and excellent long-packet EVM performance. (Courtesy: pSemi)

With new standards come new challenges. pSemi explains their PE561221 uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance.

“Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance,” says Colin Hunt, vice president of worldwide sales at pSemi.

The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules. It is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration, notes pSemi—the unique design ability to integrate RF, digital and analog components on a single die.

Volume-production parts and samples of the PE561221 are now available from pSemi. And this is just the beginning: while the PE561221 is the first product in the pSemi Wi-Fi FEM portfolio, the product roadmap includes 5 GHz Wi-Fi FEM solutions.

The folks at pSemi have been doing RF-SOI for 30 years now, and recently shipped their 4 billionth chip. For the last five years, they’ve partnered with GlobalFoundries.

Share This! Terrific Guide to All Things FD-SOI in GSA Newsletter

Manuel Sellier, Product Marketing Manager at Soitec

Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It’s in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance).

If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you’ll want to share this piece with them right away.

Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What’s more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don’t worry that this might be too technical: Sellier’s writing is thoroughly accessible (and engaging!) for anyone in the industry.

He starts with the wafer history, then quickly moves on to the features from the designer’s standpoint. And he puts it all in a business perspective. I can’t recommend this piece enough – even if you think you know everything already yourself, you’re sure to learn something new.

ST, Intento: EDA for Faster Analog Design in FD-SOI

Intento Design is working with STMicroelectronics to bring ID-XploreTM EDA software, which is aimed at solving the critical analog design challenges, to FD-SOI process nodes.

“ID-Xplore is a disruptive EDA software that accelerates analog design and migration processes by at least one order of magnitude. It reduces the cost and latency inherent to analog design. Currently, there is no similar EDA tool on the market covering the analog design challenges like ID-Xplore,” noted Dr. Ramy Iskander, CEO of Intento Design (see the press release here).

ST’s FD-SOI design expertise roots, of course, are as deep as they get. “ST’s decision to work with us confirms the relevance of our solution. We are very excited to work jointly with ST teams to take the most benefit out of FD-SOI technology leveraging ST’s pioneering leadership in this area,” continued Dr. Iskander.

“We’ve already seen the benefits of ID-Xplore in accelerating the design phase of different analog circuits, thanks to the software’s fast and accurate exploration capabilities in advanced FD-SOI processes,” said Thierry Bion, ST’s Hardware Design Director, Aerospace Defense & Legacy Division. “By facilitating IP reuse and sharing of design insights between engineers, ID-Xplore™ is helping our teams significantly accelerate new product introductions.”

ID-Xplore uses the OpenAccess database standard and is fully integrated within the Cadence design environment. The designer’s implicit and explicit knowledge is expressed as technology-independent constraints, bringing the designers back to their core expertise and creativity.

If you want to learn more, the folks over at semiwiki.com have made a number of posts on Intento Design recently. They’re really helpful in understanding what the company does, how and why:

CEO Interview: Ramy Iskander of Intento Design Edit (by Daniel Nenni) – good backgrounder on the company and product.

The Intention View: Disruptive Innovation for Analog Design Edit (by Daniel Nenni) – an excellent interview with Dr. Caitlin Brandon about how the tool works and how it aligns with and supports the way analog designers work.

A New Kind of Analog EDA Company Edit (by Daniel Payne) – Daniel Payne started his career as a circuit designer at Intel, and is now a well-known consultant/expert in the EDA world. Here he explores how ID-Xplore actually works and its “cool new automation features”.

GF’s FD-SOI Has Delivered >$2 Billion in Design Win Revenues, 50+ Clients

GlobalFoundries has announced that the company’s 22nm FD-SOI (22FDX®) technology has delivered more than two billion dollars of client design win revenue. With more than 50 client designs, 22FDX is being used in power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and IoT.

Their clients chose it for the significant reductions in power and die size relative to a traditional bulk CMOS process, says the company. 22FDX offers the industry’s lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, “…providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.”

22FDX is in early production, with yields and performance matching client expectations. A recent VLSI Research survey indicated that FD-SOI technology is seen as a complementary technology to FinFET. It’s gaining traction in application spaces such as IoT, where power consumption is important and the product life is relatively short.

“We’re only just beginning,” said GF CEO Tom Caulfied. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. We will continue to build on our momentum and look for ways to expand our reach to address the evolving needs of the industry.”

Here’s a sampling of customer quotes from the press release (read more here):

  • “At Synaptics, as we expand upon our industry-leading mobile and PC businesses to include delivering new and innovative products that address the booming IoT market, we require the best available technologies to enable us to deliver top-notch solutions including voice and multimedia processing capabilities for our customers,” said the company’s CEO, Rick Bergman. “GF’s 22FDX technology delivers a potent mix of low static and dynamic power along with excellent performance to give us a great platform for our world-class products.”
  • “As our customers increasingly demand more from their mobile experiences, our partnership with GF on its 22FDX technology is critical to differentiate ourselves in the competitive market and deliver powerful and efficient mobile SoCs,” said Rockchip CEO Min Li.
  • “Our goal has always been to provide more secure, connected experiences for drivers. Combining our leadership in radar technology with GF’s 22FDX automotive-qualified process, we are able to deliver a cost-effective, high performance, low power solution that opens new opportunities for car manufacturers to provide better experiences for drivers around the world,” said Kobi Marenko, CEO of Arbe Robotics.
  • “The automotive industry realizes that assisted driving solutions require more camera information besides Radar and Lidar, integrating information from multiple cameras. The resulting DreamChip multi-core vision processor platform, based on the 22FDX process is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives with a massively reduced time to market,” said Dream Chip Technologies CEO Jens Benndorf.
  • “With 22FDX, the value proposition for us is the potential power and area savings, two key metrics for our highly optimized LTE NB-IoT and CAT-M chipsets. In addition, leveraging the growing ecosystems of IP available in the 22FDX process helps to accelerate time to market,” said Peter Wong, CEO at Riot Micro, which designs purpose-built silicon for wireless IoT applications. (Read more about that here.)

GF adds that it is preparing to deliver 12FDX™ technology, which will provide a full node scaling benefit and improved power efficiency for a new generation of applications, from edge-node artificial intelligence and AR/VR to 5G networking and ADAS.

Leti and Soitec launch new Substrate Innovation Center – all partners welcome!

Leti and Soitec have announced a new collaboration and five-year partnership agreement to drive the R&D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level.

CEOs Emmanuel Sabonnadière (Leti) and Paul Boudre (Soitec) announcing the new Substrate Innovation Center during Semicon West ’18. (Image courtesy: Leti)

Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing.

“Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R&D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.”

Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R&D.

“Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products.”

Dolphin Showcases New EDA Tool for FD-SOI – More THINGS2DO Results

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.

THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)

“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”

The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.

Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.

The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.

Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.

Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”

See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF’s 22FDX.

Maker Alert: FD-SOI at Heart of $50 Sony SPRESENSE™ Board for IoT

The MCU at the heart of Sony’s new smart-sensing SPRESENSE™ for IoT is built on FD-SOI. Why? Low operating voltage and low power consumption, of course! Sony’s got two cool new products going on sale in July 2018: the SPRESENCE main and extension boards for IoT applications, equipped with a smart-sensing processor (read the full press release here). A CXD5602PWBCAM1 camera board for sensing cameras will go on sale in August. All were on display at the SF Maker Fair ’18, where they were an instant hit.

Here are the main features of Sony’s CXD5602 MCU for IoT, which is built on FD-SOI. (Courtesy: Sony Semiconductor Solutions)

The main board (it’s open source, btw) will run about US$50. You’ll find the specs and main features here.

Spresense is powered by Sony’s FDSOI-based CXD5602 MCU (ARM Cortex-M4F × 6 cores), with a clock speed up to 156 MHz. The main board utilizes a multi-CPU structure equipped with Sony’s state-of-the-art GNSS (Global Navigation Satellite System – which they talked about at the most recent SOI Symposiums in SF and Tokyo) receiver. A variety of systems for diverse applications, including drones, smart speakers, sensing cameras and other IoT devices, can be built by combining these boards and developing the relevant applications.

The new board can be used to control a drone, for example, using GPS positioning technology and a high-performance processor, voice-controlled smart speakers, low-power consumption sensing cameras and other IoT devices, etc. It can also be combined with various sensors for use in systems that detect errors in production lines on the factory floor.