To make cars more comfortable, convenient, safe and secure, leading car makers such as DaimlerChrysler, BMW, Ford, GM and VW are using In-Vehicle Networking (IVN) systems that can consist of anywhere from 10 to 100 chips. The primary IVN networking protocol, Controller Area Network or CAN, is used throughout the car in body, chassis and […]
Many defense electronics contractors have a need for advanced signal processing solutions that can fit into space constrained platforms, such as the new, smaller Unmanned Aerial Vehicles (UAVs), as well as in pods under manned aircraft and smaller ground vehicles. The signal processing systems on all these platforms must be able to function under difficult […]
Casio calls its new Atomic-Solar G-Shock watch “the hottest G-Shock available”. As heralded in a recent press release, “The toughest watch in the world is now the smartest watch in the world.” It gets its power from the sun and its time from the Atomic Clock in Fort Collins, Colorado.
When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management. The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves […]
Although the basic principles of Silicon-On- Insulator (SOI) technology are simple, the ramifications are far reaching. The use of SOI reduces parasitic capacitance around embedded circuit elements, reduces leakage currents, and enhances isolation between circuit elements. These improvements affect switching speed, threshold voltage, power consumption, noise, and the minimum space needed between components embedded in […]
Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September. The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.” The program, […]
In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar […]
Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, […]
A preliminary public version of the “EUROSOI State of the Art Report” is now available at www.eurosoi.org. It compiles the contributions of more than 150 researchers/experts from 14 European countries active in SOI technology, devices and systems. A listing of current European and national SOI projects is also available on the site •
SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS devices and circuits through modeling.” He thereby joins such industry luminaries as Andrew Grove and Bernard Meyerson in receiving one of the Electron Devices Society’s (EDS) and IEEE’s highest honors.