CELLs Multiply

IBM, Sony/SCEI and Toshiba are actively encouraging the proliferation of CELL applications   The most celebrated of Cell applications, Sony’s PlayStation® 3, is due out next spring. In the meantime, the SOI-based Cell Broadband Engine (CBE) microprocessor, as it is officially known, is getting a big push from its joint developers: Sony Computer Entertainment, Inc. […]

SOI in Japan: Full Circle

SOI got its start in Japan. Now in a raft of new applications, its home again   Japan’s NTT launched the worldwide SOI revolution 27 years ago when it developed the SIMOX (Separation by IMplanted OXygen) process, and gave the first demonstration of an SOI device. Then, with the advent of wafer bonding and Smart […]

Xbox® 360 Debuts New Gaming Generation

Microsoft’s custom PowerPC chip by IBM is based on SOI   Microsoft’s Xbox 360, which is expected to fly out of the stores this holiday season, has some very impressive figures to cite. The three-core PowerPC-based CPU, custom-made for Microsoft by IBM, boasts one teraflop of floating-point performance.

Fab Floor Tip: Running SOI in RTP

A quick guide to successful rapid thermal processing of SOI wafers Some engineers have indicated that they encounter challenges when running SOI wafers in rapid thermal processing (RTP). Why is this specific to SOI?

Dawn of a New Age of Chip Technology

Following a long and distinguished career at Sony and Hitachi, an industry visionary reflects on what’s to come   For about the past four decades, chip progress was achieved by “shrinking”. Things were simple because three factors – speed, power and density – were improved simultaneously. In the case of advanced nano devices, leakage current, […]

Achieving High Throughput Inspection of Multiple SOI Wafers

Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts. The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and […]

Soitec and SEZ Collaborate to Speed Industrialization of sSOI

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in […]

NIST Nanowire Transistors on SOI

New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel […]

MIRAI-ASET Working on SGOI and GeOI

3,1 times greater hole-mobility observed in ultra-thin GeOI   MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They […]

Soitec President Elected to SEMI Board

Auberton-Hervé joins other prominent industry leaders in representing the interests of material suppliers and equipment manufacturers   SEMI recently announced the appointment of André-Jacques Auberton-Hervé to its International Board of Directors. Auberton-Hervé was unanimously elected by the 20 voting members of the association’s board at its recent annual policy and planning meeting. In his announcement, […]