Gartner Dataquest has been conducting research on the SOI wafer market trend since 1995. Its results indicate that SOI wafer demand achieved a compound annual growth rate (CAGR) of 33% over the decade between 1995 and 2005.
Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond. Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.
Toshiba has successfully developed a high-performance, high-density, low-cost 128Mb FBRAM. FBRAM is Random Access Memory (RAM) with a Floating Body Cell (FBC). It is a capacitor-less DRAM cell consisting of a MOSFET on an SOI wafer. Data “1” and Data “0” are distinguished by the hole density in the floating body of the MOSFET.
Embedded DRAM on SOI is set to proliferate at the 45nm node. Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).
The co-inventor of Z-RAM explains the technology. As a Z-RAM – zero capacitor RAM – memory technology bit cell uses only a transistor plus the floating body effect inherent in SOI processing (see Figure 1), it typically measures only 15-20F² (where F is the technology minimum feature size).
As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices. It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report  on the importance of the BOX thickness with […]
Soitec is now sampling 25nm-thick UT-BOX. Advanced SOI with ultra thin buried oxide (UT-BOX), in which the insulating BOX layer is less than 50nm thick, brings additional benefits to SOI CMOS architecture. It enables: • electrostatic control of the device by back biasing, allowing ultra-low power operation through dynamic Vt control [1, 2]. • the […]
The PS3, Wii and Xbox 360 CPU design teams all chose SOI. Here’s why. Design challenges (Read the Cell overview paper by Kahle et al on the IBM website) Achieve 100 times the PlayStation®2 performance. Joint developers IBM, Sony Group and Toshiba needed to co-optimize the chip area, design frequency, and product operating voltage, creating […]
Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity. The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version […]
A lead developer of Hitachi’s µ-chip explains the SOI benefits. By using SOI, we could make an ultra-small RFID chip. In particular, its excellent isolation capability enabled successful miniaturization of the analog circuits in the front-end of the part. Also, BOX (Buried OXide) acts as an etch-stop layer in the self-controlled process, resulting in an […]