ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.
Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?
Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.
It’s an ECSEL project (ECSEL is the Electronic Components and Systems for European leadership, an EU-driven, public-private partnership that funds innovation). The budget is 103M€ for a European consortium of 27 partners from 7 different countries. The topic is “Ultra-low power computing solutions for automotive and aeronautics using all the range of FD-SOI technologies”, and Soitec is the project leader.
ASN: Why is it needed?
FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require a power consumption equivalent to that of 50 to 100 computers running continuously (without taking into account the car propulsion).
The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.
The FD-SOI solutions developed in OCEAN12 offer a palate of different solutions to this challenge. Indeed the solutions will come with components that are more performant for data processing (including Artificial Intelligence), much more energy efficient, more highly-integrated and smaller to fit in embedded systems like in autonomous cars, reliable, and enabling safe connectivity.
The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.
ASN: What are the project goals?
FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption for autonomous driving in the automotive industry.
As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of components up to the system and end-user application levels. We will show that the technology is useful for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.
The OCEAN12 project goals stand on three pillars:
ASN: Can you tell us more about the demonstrators? When will we see them?
FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:
ASN: Can you tell us more about the partners?
FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.
The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.
Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer (GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.
In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design&Reuse.
All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their field of activity. Their contributions are essential for the success of the project.
ASN: What is the timetable?
FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.
ASN: Can you clarify the funding structure?
FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M. However, the majority of the budget is paid by the participating companies and organizations.
These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems. For example, we saw how well it worked with RF-SOI, which also had European and national funding, and is now in every smartphone made in the world.
To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.
The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai.
Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums.
The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website — click here to get them.
Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.
Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes.
Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.
Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips.
The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF.
All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.
Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Key takeaway #2: If you need a Goldilocks process node – where you’ll get just the right balance between active power, unit cost and investment – look to FD-SOI. And, btw, the IP landscape has improved dramatically. Those were just some of the great points made by Huibert Verhoeven (shown above), GM/SVP of Synaptics’ IoT Division in his talk at the recent SOI Symposium in Silicon Valley.
BTW, if you missed part 1 of our coverage —Silicon Valley SOI Symposium a Huge Success. Key Takeaways (Part 1) Here. – you’ll want to be sure to read it, too. Almost all of the presentations are now posted on our website – click here to access them.
In this post here, we’ll cover presentations by Synaptics, GlobalFoundries, STMicroelectronics, Anokiwave and Dolphin Integration. It was a really full, day, so be sure to stay turned for Part 3 of our coverage to follow shortly: it will highlight the remaining presentations and panel discussions.
Synaptics’ Verhoeven’s presentation Revolutionizing User Experience Through Secure Neural Network Acceleration at the Edge was about Smart Home and using SOI. Synaptics is a human interface (HMI) company that’s been doing neural networks since 1986. They’ve always been on the leading edge, from their first shipment of PC touchpads to becoming a dominant force in all things HMI today: they now ship over a billion units annually.
They currently have SOI products shipping with dedicated neural networks for voice, he said. European [privacy] regulations have played a part in driving their use of SOI, as have challenges regarding power and heat. Things are getting smarter at the edge. For example, not only do users want their coffee machine to offer the usual morning espresso, Synaptics says that the next step is for your coffee machine to recognize you’re looking extra tired and ask if you might want a double?!
For them Smart Home and multi-modal applications are the primary area of interest, as well as some automotive. Although their biggest customers have resources, others need guidance. Voice is a critical component, but now you also need video and display.
Why SOI? Their HMI vision requires low power, significant computation and dedicated neural network hardware, explained Verhoeven, so FD-SOI with RF meets their needs. “22nm SOI is a Goldilocks IoT Process Node,” he proclaimed. It gets the combination of active power, unit cost and investment just right. What’s more, he said, “The IP landscape has improved dramatically. Our choice of SOI was not an accident.” Be on the lookout for more products leveraging FD-SOI over the next six months, he concluded.
At this point on SOI, they’ve got 1 TOPS products with dedicated NPU for speakers, soundbars, Wi-Fi mesh, appliances, STBs and smart displays. These products have voice and sensor real-time (RT) AI. Next up is >4 TOPS on SOI with dedicated NPU, targeting STBs and smart displays with voice, video, imaging and RT AI.
“Our clients are at the forefront of changing the world,” declared Mark Granger, VP of the Automotive Product Line at GlobalFoundries. His presentation, Capturing High Growth Market Opportunities with SOI, detailed how mobility, automotive and IoT are the growth markets for SOI. So not unsurprisingly, GF’s 22nm FD-SOI technology, 22FDX, is seeing particular traction in mobile, edge, wearables and automotive.
They’ve got twice as many tape-outs this year as they did a year ago, he noted. GF’s SOI portfolio includes 22FDX®, 45RFSOI and 8SW/7SW RF SOI for 5G/mobility; 22FDX for automotive (fully qualified for automotive Grade 2, with Grade 1 on the way); and 22FDX, 130RFSOI and 8SW/7SW RF SOI for IoT.
GF has announced a stream of good news recently:
You might have heard about the Dolphin Integration news, as we covered it recently here at ASN (if not, be sure to read it here). Dolphin’s IP and methodology solutions address energy efficiency challenges. Automated transistor body biasing adjustment can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. At the Silicon Valley event, Dolphin Integration CEO Philippe Berger provided additional information in his talk, FD-SOI IP Platform for Energy-Efficient IoT SoC.
In another GF-related talk, Nitin Jain, the CTO of longtime GF RF-SOI customer Anokiwave presented Unleashing the mmWave Phase Array Using SOI for 5G & Satcom. Anokiwave is a fabless semi IC company (you’ll find a good technical discussion of mmWave phase array written by their Chief Architect here). They do active antennas (aka phased array), something the military’s done for a long time, but now Anokiwave is bringing it to new markets and applications including radar, satcom and 5G. What they’ve been able to do is planarize the active antennas. They use GF’s 45RFSOI process technology for phased array systems because of the cost, performance, scalability and system enhancements it enables. 45RFSOI, he explained, is ideal for beam-forming FEMs (including the switches, LNAs and PAs). The move to 5G/mmWave is going to require a lot of antennas, so these Anokiwave ICs are headed to high volumes, concluded Jain.
As Roger Forchhammer, Director of Business Development at STMicroelectronics pointed out in his presentation, Automotive FD-SOI Microcontrollers with Embedded PCM, ST pioneered FD-SOI (and that was almost a decade ago, btw). Then in February 2019, they announced a world first: they’d begun sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on embedded Phase-Change Memory (ePCM) to 10 alpha customers. These MCUs target powertrain systems, advanced and secure gateways, safety/ADAS applications, and vehicle electrification.
(In case you want technical details, the breakthrough ePCM eNVM was first presented at IEDM in December 2018 – you can get the presentation that accompanied the paper, Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller Applications embedding 16MB Phase Change Memory, from the ST website.)
In his Silicon Valley presentation, Forchhammer said they’re now doing Stellar, a whole family of automotive products on FD-SOI. To do it, they’d taken an existing device and moved it to 28nm FD-SOI with ePCM, which they manufacture at their fab in Crolles, France. A major advantage for automotive he cites is that in software updates it’s bit-level programmable. “ST is fully behind FD-SOI,” he concluded, adding that we’re see more automotive as well as IoT products coming soon.
Well folks, that’s all for this post. We’ll finish up our coverage of the SOI Consortium’s 2019 Silicon Valley Symposium in the next ASN post (there was so much to cover!). So please stay tuned.
Two of the big, recent breakthroughs in memory technology – eMRAM and ePCM – have gotten their start in volume manufacturing on 28nm FD-SOI. In conjunction with the 2019 IEEE International Memory Workshop, SOI Consortium members Leti and Applied Materials have teamed up to give a technical program to explore short-term and long-term memory solutions. While the workshop is not specific to SOI, given the recent foundry announcements about ePCM and eMRAM for FD-SOI, the organizers predict it will be of particular interest to those following the greater SOI ecosystem. The event takes place at the end of the Sunday IMW tutorial day, starting at 5:30pm at the Hyatt Regency in Monterey, CA. Please see this page for the program and registration information.
Here is the program:
Jean-Eric Michallet, Head of Leti’s Microelectronics Components Department, Silicon Component Division is one of the organizers. Here is his overview:
FD-SOI is expected to be a long-lived technology. It enables planar CMOS scaling and accommodates a great deal of More-than-Moore developments where its ability for low power and great analog performance can make a difference for IoT, Automotive, Machine Learning or 5G applications. But to do this it requires a high-performance and cost-effective non-volatile embedded memory option. The incumbent Flash cell is reaching the end of its roadmap due to the difficulty of shrinking the bitcell and manufacturing, as well as the finished wafer cost increase. Back-end integrated Random Access Memory in advanced CMOS process has been explored for many years now as a competitive solution for fast-write and low-voltage non-volatile embedded memories. Foundry availability of embedded Magnetic RAM and Phase Change RAM for FDSOI 28nm platforms has been announced recently, showing that these technologies have now reached industrial maturity. CEA-Leti and Applied Materials invite you to attend a technical program to explore short-term and long-term memory solutions, from early research to industrialization.
Registration is open, free, and available to all IMW attendees, and others. However, as seating is limited and as we have already several participants pre-registered, registration is by invitation only and early registration is recommended. If you are interested, please email Jean-Eric Michallet.
The event is presented in conjunction with the 2019 IEEE International Memory Workshop, to be held on Sunday, May 12th, 2019, Hyatt Regency, Monterey CA, starting at 5:30 pm.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.
IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.
Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.
The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.
I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.
I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.
One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.
Mark provided a GF link for more information:
Here is the link to our Automotive resources:
One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.
Here is the press release:
Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process
Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs
MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.
“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”
“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”
“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:
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About the Author
Daniel Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”. He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.
The world’s SOI wafer leader, Soitec is posting strong sales and issuing a steady stream of compelling announcements. This is clearly good news for everyone in the SOI ecosystem, as the outlook for the various families of SOI wafers is excellent.
Soitec CEO Paul Boudre told ASN, “I’m excited because of the fundamentals behind the growth. Reaching down the supply chain gives us the ability to help our customers with the next generation. We’re not in a technology push, but in a technology pull. It’s long-term growth we’re seeing.”
Soitec has brought people from the device side into the company to better understand the solutions customers need, he said. They’re talking to the carmakers, telcos and more, working one-on-one with them to understand the constraints and the problems they are trying to fix, in order to deliver a solution based on the Soitec product roadmap. Boudre is particularly excited about 5G. It’s not just new handsets and systems: the entire infrastructure will require a massive upgrade, across which Soitec has a role to play supplying SOI wafers.
They also have other SOI and engineered substrates for specific markets like filters, displays, imaging and power. He adds that they’re seeing nice growth in SOI wafers for photonics, driven by cloud computing, and for smart power in markets like automotive and white goods.
Here’s a roundup of some recent developments. Chips made on RF-SOI wafers are in every mobile phone made on the planet these days, so lets look at what they’re doing there first. We’ll follow that with an update on the surge of activity on FD-SOI wafers.
It’s no secret that the runaway success of RF-SOI for front-end modules (FEMs) in mobile phones has stretched wafer capacity mightily. To help address this, in February 2019 Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. The two companies redefined their manufacturing and licensing relationship to better serve to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics.
Since the two companies signed their original licensing and technology transfer agreement in May 2014, Simgui has mastered Soitec’s Smart Cut™ proprietary process to deliver world-class RF-SOI and Power-SOI products. Simgui’s strategic partnership with Soitec allows them to use the same tools and processes to deliver the same products meeting the same specifications.
Simgui has invested in their Shanghai fabrication line in order to double annual 200mm SOI wafer production capacity from 180,000 to 360,000. The fab is production ready, having been qualified by multiple key customers inside and outside China.
Simgui CEO Dr. Jeffrey Wang notes, “China has design, wafer manufacturing and good momentum in the IC industry. We are committed to our strategic partnership with Soitec to keep advancing SOI as China’s key differentiator.”
China Mobile’s interest in the SOI ecoystem is clear: they’ve presented at the SOI symposia in Shanghai for two years running now. In a February 2019 press release, Soitec announced that they’ve joined the China Mobile 5G Innovation Center – and they’re the first materials supplier to do so. The China Mobile 5G Innovation Center is an international alliance chartered to develop 5G communication solutions for China, the world’s largest wireless communications market with 925M mobile subscribers. The Center aims to accelerate the development of 5G by establishing a cross-industry ecosystem, setting up open labs to create new products and applications, and fostering new business and market opportunities.
Soitec’s RF-SOI wafers have been critical in the deployment of 4G communications, and the opportunity in 5G is even bigger. Plus the company’s FD-SOI wafers enable the technology that brings unique RF performance, making it an ideal solution for many applications including mmWave communications such as 5G transceivers. They are also enabling full RF and ultra-low-power computing integration for IoT and edge computing.
In January 2019, Soitec announced that they have expanded their collaboration with Samsung Foundry on the FD-SOI wafer supply, securing the high-volume Samsung needs to meet industry’s current and future demands in consumer, IoT and automotive applications. The agreement is built on the existing close relationship between the companies and guarantees wafer supply for Samsung’s FD-SOI platform starting with the 28FDS process.
“Samsung has been committed to delivering transformative industry leading technologies,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “FD-SOI is currently setting a new standard in many high-growth applications including IoT with ultra-low-power devices, automotive systems such as vision processors for ADAS and infotainment, and mobile connectivity from 5G smartphones to wearable electronics. Through this agreement with Soitec, our long-term strategic partner, we hope to lay the foundation for steady supply to meet high-volume demands of current and future customers.”
“This strategic agreement validates today’s high-volume manufacturing adoption of FD-SOI,” said Christophe Maleville, Soitec’s Executive Vice President, Digital Electronics Business Unit. “Soitec is ready to support Samsung’s current and long-term growth for ultra-low power, performance-on-demand FD-SOI solutions.”
In February 2019 Soitec announced they’d become a strategic partner in Silicon Catalyst’s start-up incubator. Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses.
Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.
“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions.”
Pete Rodriguez, CEO of Silicon Catalyst said, “Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog/mixed-signal performance.”
And finally, jumping back a few months, at the end of 2018 Soitec announced that their SOI wafers are at the heart of a new Renesas SOTBTM energy harvesting chipset, opening a self-powered future for IoT devices. SOTB is how Renesas refers to its FD-SOI technology.
(BTW, here at ASN we’ve been covering the work that Renesas has quietly done on this technology since 2005 (!). And we did a piece about an EETimes Japan article back in 2015 that revealed the launching of the 65nm work. )
Soitec supports the Renesas SOTB chipset with a special version of its FD-SOI wafer product line. The new Renesas SOTB-based chipset overcomes the energy constraints of IoT devices and reduces the power consumption to approximately one-tenth that of the existing products in the market today. That makes the chipset perfectly suited for extreme low-power, maintenance-free and energy harvesting applications including wearable devices, smart home applications, smart watches, portable appliances, infrastructure monitoring systems, industrial, business, agricultural, healthcare, as well as health and fitness apparel, shoes, drones and more.
Renesas has developed its energy harvesting chip using its unique SOTB 65nm process technology that achieves both low active current of 20 μA/MHz and deep standby current of 150 nA. As a result, Renesas’ SOTB chipsets offer enhanced control of the transistor electrostatics and reductions in both the standby and active currents to levels never before achieved. Additionally, Renesas has successfully delivered the dopant-less channel to suppress Vth variability for the ultra-low voltage operation, and the ultra-low power back bias control to reduce the standby current at the same time.
“To spur innovations in IoT and consumer applications, we have integrated our exclusive energy-harvesting SOTB technologies into our Energy Harvest Controller,” said Mr. Toru Moriya, Vice President of Renesas’ Home Business Division, Industrial Solutions Business Unit. “We are confident that our SOTB technology built on Soitec’s ultrathin substrates can deliver unmatched capabilities for developing maintenance-free IoT devices that never require power supply or replacement, giving rise to a new IoT global market based on endpoint intelligence.”
The new R7F0E Embedded Controller is the first device based on Renesas’ SOTB technology. Developers can now design applications that need no battery or recharging. The R7F0E features: an Arm® Cortex® -M0＋; operating frequency up to 32 MHz, and up to 64 MHz in boost mode (that’s body bias in action!); memory of up to 1.5 MB flash, 256 KB SRAM; and active current consumption while operating at 3.0V of just 20 µA/MHz, and in deep standby of 150 nA with real-time clock source and reset manager. As of this writing, Renesas indicates it’s engaging select customers through July 2019, with mass production in 4Q19. Read more about the R7F0E on the Renesas website.
GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019.
As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.
The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.
“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”
“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”
As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of.
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*A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago:
Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.
For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering’s Ann Steffora Mutschler from a couple years ago.