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27 April 2018: FD-SOI Training Day – Milpitas, CA

Training day on analog, RF, high speed, millimeter wave and mixed-signal design techniques in FD-SOI technologies

Tutorial registration fee: USD 485.00 (incl. training book, breakfast, lunch box and breaks)

Limited places available, first come first save!

Organizer: Andreia Cathelin, STMicroelectronics
Mentors: Carlos Mazuré, Giorgio Cesana, SOI Industry Consortium

World renowned professors and experts from industry will deliver a series of four training sections of 1.5hrs each, dedicated to energy efficient and low power low voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design.

Attendees will learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities, that further enhance the excellent analog/RF performances of these devices.

Each section of this training day will take the participants through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies and 28nm, 22nm nodes and beyond. The design examples will cover basic building blocks through SoC implementations. 


PROGRAM & Abstracts

7.30 – 8.30 breakfast and registration

8.30- 10.00
Andreia Cathelin, Fellow, STMicroelectronics Crolles, France
FDSOI specific design techniques for analog, RF and mmW applications

10.00 – 10.15 coffee break

10.15 – 11.45
Frank Zhang, Principal Member of Technical Staff, Globalfoundries
Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications

11.45 – 13.00 lunch

13.00 – 14.30
Bora Nikolic, Professor, UC Berkeley, Berkeley, USA
Energy-Efficient Design in FDSOI

14.30-14.45 coffee break

14.45 – 16.15
Sorin Voinigescu, Professor, University of Toronto, Toronto, Canada
mm-Wave and Fiber-optics Design in FD-SOI CMOS Technologies

16.15 – 17.00
General Q&A session and closing remarks

Location of the Training:  Crowne Plaza San Jose, Milpitas.