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27 April 2018: FD-SOI Training Day – Milpitas, CA


Training day on analog, RF, high speed, millimeter wave and mixed-signal design techniques in FD-SOI technologies

Organizer: Andreia Cathelin, STMicroelectronics
Mentors: Carlos Mazuré, Giorgio Cesana, SOI Industry Consortium

World renowned professors and experts from industry delivered a series of four training sections of 1.5hrs each, dedicated to energy efficient and low power low voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design. Attendees learned about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities, that further enhance the excellent analog/RF performances of these devices. Each section of this training day took the participants through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies and 28nm, 22nm nodes and beyond. The design examples covered basic building blocks through SoC implementations.

TRAINING PROGRAM & ABSTRACTS

(complete decks will not be published)


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