During the full day training on “Designing with FD-SOI Technologies”, world-renown professors and scientists from UC Berkeley, Stanford, Toronto and Lund Universities and STMicroelectronics will give instruction on FD-SOI specific design techniques in the domains of analog, RF, mmW and mixed signal, as well as ultra-low power memories, energy efficient digital and analog-mixed signal processing designs.
Andreia Cathelin, STMicroelectronics
Carlos Mazuré and Giorgio Cesana, SOI Industry Consortium (Mentors)
Auditorium “Palace”, South Lobby at Samsung Semiconductor Inc., 3655 N 1st St, San Jose, CA 95134
You will leave the soiconsortium.org website. Registration will be processed through the registration platform azavista.com.
8.00 a.m. – 8.30 a.m.: Breakfast
8.30 a.m. – 9.30 a.m.:
Andreia Cathelin, Fellow, STMicroelectronics Crolles, France:
FDSOI Short Overview and Advantages for Analog, RF and mmW Design
9.30 a.m. – 10.30 a.m.:
Sorin Voinigescu, Professor, University of Toronto, Toronto, Canada:
Unique Circuit Topologies and Back-gate Biasing Scheme for RF, mm-wave and Broadband Circuit Design in FDSOI Technologies
10.30 a.m. – 11.00 a.m.: Break
11.00 a.m. – 12.00 p.m.:
Joachim Rodrigues, Professor, Lund University, Lund, Sweden:
Design Strategies for ULV memories in 28nm FDS-SOI
12.00 p.m. – 1 p.m.: Lunch
1 p.m. – 2 p.m.:
Bora Nikolic, Professor, UC Berkeley, Berkeley, USA :
Energy-Efficient Processors in 28nm FDSOI
2 p.m. – 3 p.m.:
Boris Murmann, Professor, Stanford University, Palo Alto, USA:
Pushing the Envelope in Mixed-signal Design using FD-SOI
End of Tutorial Day.