10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)
FD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.
There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we have a rundown of the top SOI-based advanced CMOS papers. In Part 2, we’ll cover papers on future device architectures. In Part 3 we’ll look at the papers on MEMS, NEMS, sensors and more.
Summaries culled from the abstracts follow.
The FD-SOI Papers
9.1: FD-SOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node.
Q. Liu et al (STMicroelectronics, CEA-LETI, IBM, Soitec)
In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)
In this work, researchers from STMicroelectronics and the IBM Technology Development Alliance demonstrate the successful implementation of strained FDSOI devices with LG, spacer & BOX dimensions scaled to 10nm feature sizes.
Two additional enabling elements for scaling FD-SOI devices to the 10nm node are reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 µA/µm for NFET at Ioff=1 nA/um (the highest performing FD-SOI NFET ever reported), and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 µA/µm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL are also reported.
![[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14. (Courtesy: ST et al, IEDM 2014)](https://i2.wp.com/advancedsubstratenews.com/wp-content/uploads/2014/12/ST_IEDM14_9.1_Table1_FDSOI_10nm.png)
[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14.
(Courtesy: ST et al, IEDM 2014)
B. De Salvo et al. (Leti, ST, IMEP, IBM, Soitec)
This paper presents an original multi-level evaluation methodology for stress engineering device design of next-generation power-efficient devices. Ring oscillator simulations showed that a dynamic power gain of 50% could be achieved while maintaining circuit frequency performance thanks to the use of efficient mobility boosters. Thus a clear scaling path to achieve high-mobility, power-efficient sub-14nm FDSOI technologies has been identified.
3.4: Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-Voltage Range SRAM Operation in 28nm UTBB FD-SOI
O. Thomas et al (UC Berkeley, ST)
This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than 100fA/bitcell are measured in a 140kb programmable dynamic SRAM. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.
27.5: New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration
C. Fenouillet-Beranger et al (Leti, ST, LASSE)
For the first time the maximum thermal budget of in-situ doped source/drain state-of-the-art FD-SOI bottom MOSFET transistors is quantified to ensure transistors stability in Monolithic 3D (M3D) integration. Thanks to silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Thanks to in-depth morphological and electrical characterizations, it shows very promising results for high performance Monolithic 3D integration.
9.2 Future Challenges and opportunities for Heterogeneous process technology. Toward the thin films, Zero intrinsic Variabiliiy devices, Zero power Era (Invited)
S. Deleonibus et al (Leti)
By 2025, 25 % of the World Gross Domestic Product will depend on the development of Information and Communication Technologies . Less greedy device, interconnect, computing technologies and architectures are essential to aim at x1000 less power consumption.
IBM’s SOI-FinFET, eDRAM and 3D Papers
32.1: Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme
H. Tsai et al (IBM)
These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)
High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision. In this paper, IBM researchers present the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node.
(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)
Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.
Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)
3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News)
C-H. Lin et al (IBM)
The IBM team presents a fully integrated 14nm CMOS technology featuring FinFET architecture on an SOI substrate for a diverse set of SoC applications including high-performance server microprocessors and low-power ASICs. A unique dual workfunction process optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel and without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. Because the technology is envisioned for use in SoC applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom than ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.
The SOI FinFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.
16.1: First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications
P. Hashemi et al (IBM)
Strained SiGe FinFETs are a promising PMOS technology for the 10nm technology node and beyond, due to their excellent electrostatics and built-in uniaxial compression. Yet while SiGe FinFETs with moderate germanium (Ge) content have been characterized, little data exists on FinFETs with high Ge content. And, what little data does exist is mostly focused on relaxed or strained pure Ge. For the first time anywhere, IBM detailed CMOS-compatible, low-power and high-performance SiGe PMOS FinFETs with more than 50% Ge content. The devices feature ultra-narrow fin widths – down to 3.3 nm – which provide excellent short-channel control for low-power applications. Using a Si-cap-free passivation process, they report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1e13 cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. They demonstrated the highest performance ever reported (Ion=0.42mA/µm and Ioff=100nA/µm) for sub-20nm PMOS FinFETs at 0.5 V.
19.4: 0.026µm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications
C. Pei et al (IBM)
This paper presents the industry’s smallest eDRAM based on IBM’s 22nm (partially depleted) SOI technology, which has been recently leveraged for IBM’s 12-core 649mm2 Server Processor POWER8™. It summarizes the n-band resistance innovations, and reports for the first time the asymmetric embedded stressor, cavity implant and through gate implant employed in 22nm eDRAM technology. The fully integrated 256Mb product array has demonstrated capability of 1.4ns cycle time, which is significantly faster than any other embedded DRAM.
14.6: Through Silicon Via (TSV) Effects on Devices in Close Proximity– the Role of Mobile Ion Penetration – Characterization and Mitigation
C. Kothandaraman et al (IBM)
The research team identified and studied a new interaction between TSV processes and devices in close proximity, different from mechanical stress. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. They then presented an improved process, confirmed in test structures and DRAM.
RF-SOI
18.4: Technology Pathfinders for Low Cost and Highly Integrated RF Front End Modules
C. Raynaud (Leti)
This paper highlights the challenges related to the increasing number of modes (GSM, WCDMA, LTE) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multimode multi–band RF Front End modules.
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This is the 1st post in a 3-part series. Part 2 (click here to read it) of ASN’s IEDM ’14 coverage looks at papers covering SOI-based future device architectures. Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.
Two additions to Altatech equipment lines: 10x faster ultra-thin film deposition; Doppler nano-defect inspection captures true sizing and positioning
The Orion Lightspeed™ inspection system by Altatech (a division of Soitec) pinpoints the true size and location of nano-scale defects inside compound semiconductor materials and transparent substrates
Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies used for R&D and manufacturing of semiconductors, LEDs, MEMS and photovoltaic devices.
The company’s newest inspection system, the Orion Lightspeed™, is capable of pinpointing the size and location of nano-scale defects inside compound semiconductor materials and transparent substrates (see press release here). The new system helps to ensure the quality control of high-value engineered substrates used in several fast growing markets including high-brightness LEDs, power semiconductors and 3D ICs. Inspection is based on Altatech’s patented synchronous Doppler detection™ technology, which determines the exact size and position of defects by making direct physical measurements with resolution below 100 nm. This provides true defect sizing, as opposed to other types of inspection equipment on the market that make indirect measurements using diffracted light to calculate approximate defect sizes. It handles 200mm or 300mm substrates, with throughput of 85 and 80 wafers per hour, respectively. Beta systems have already been installed at customers’ facilities and are demonstrating excellent performance. Shipments of production units are scheduled to begin in April 2015.
The new AltaCVD 3D Memory Cell™ is the latest member of Altatech’s AltaCVD line, designed to deposit ultra-thin semiconductor films that enable the manufacturing of high-density, low-power memory ICs used throughout mobile electronics (see press release here). The new system performs atomic-layer deposition 10 times faster than conventional atomic-layer deposition (ALD) systems, helping to meet global market demands for both high-volume production and cost efficiency in fabricating advanced memories. The system is currently demonstrating its unique capabilities and performance at one of Altatech’s key customers. Production units are available.
SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications
ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.
We learned all this and much more during the very successful 2014 IEEE S3S Conference.
The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.
Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.
S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)
The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.
The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.
Sub-Threshold Microelectronics
The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.
3D Integration
The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).
Key Fully-Depleted SOI Technical results
Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.
STMicroelectronics and CEA-Leti gave us a wealth of information on:
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From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)
How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).
- How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).
The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).
In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.
From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)
The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.
On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.
Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).
Join the conference in 2015!
Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.
The organizing committee is looking forward to seeing you there!
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Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory. He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT. Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices. Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.
Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors. He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999. As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials. As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes. He has authored or co-authored over 50 papers and holds over 10 patents.
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*RO = ring oscillator
Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)
(For best rates, register by September 18th.)
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Photo Credit: Catherine Allibert
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
Conference program
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
Please take a moment to learn more about our conference by browsing our website or downloading our advance program.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
- Photo Credit: Catherine Allibert
Engaging Kleinman (ex-GF/Xilinx) piece on LinkedIn Advocates for 28nm FD-SOI
A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI. Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), “…in my book 28nm FD-SOI offers very similar performance/power characteristics to 20nm bulk silicon.” Kleinman’s currently SVP at HMicro, which is doing SOC solutions for demanding wireless apps and IoT. He’s clearly got the street creds, arriving there by way of upper management at GlobalFoundries, Xilinx, HP, etc., having started out with a Stanford MSEE. A good read – recommended.
SST article details Leti’s Monolithic 3D presentation at Semicon West ’14
An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for scaling’.” Cronquest puts the big picture in perspective, while providing plenty of technical information. He ends by reminding readers that this and other key work will be further detailed at the IEEE S3S Conference (S3S = SOI + 3D + Subthreshold Microelectronics) October 6-9, 2014 at the Westin San Francisco Airport (see the conference website here).
Leti’s Monolithic 3D Highlighted in IEEE Spectrum
An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to foundries,” she says in the article. “I feel very confident when I say that.” In case you missed it, leaders of Leti’s 3D team also published a very informative piece right here in ASN – click here to read it.
2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May
IEEE International
SOI-3D-Subthreshold Microelectronics Technology Unified Conference
6-9 October 2014
Westin San Francisco Airport, Millbrae, CA
The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).
Photo Credit: Catherine Allibert
Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.
The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.
The 2014 edition of the conference already promises a rich content of high-level presentations.
Program
The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.
Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.
On the same webpage, more information is given about the various dedicated sessions.
There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.
Scope of the conference
The Committee will review papers submitted by May 26 in the three following focus areas of the conference:
- Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.
- Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.
- 3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.
Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.
Location
The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.
Important dates:
Paper submission deadline: 26 May 2014
Notification of acceptance: 23 June 2014
Short course date: 6 October 2014
Conference date: 6 – 9 October 2014
More details are available on the S3S website.
Photo Credit: Catherine Allibert
U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials
The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates matching those of more conventional CVD techniques. The system will be used by both internal and external researchers in fabricating a broad range of semiconductor-based devices including leading-edge CMOS transistors, MEMS, ICs built with the latest in through-silicon-via (TSV) technology, advanced LEDs and solar cells. Altatech is a subsidiary of Soitec (the world leader in SOI wafer manufacturing). AltaCVD systems have been used extensively in R&D and pilot production facilities throughout Europe; however, the University of Washington’s order represents the first such system to be delivered to a North American university R&D and pilot production facility.
Dr. Michael Khbeis, acting director of the WNF, said, “The AltaCVD system provides a unique capability that enables researchers to deposit conformal metal films for TSV applications as well as metal oxides and nitrides for high-k dielectrics and piezoelectric materials. The higher deposition rate enabled by pulsed CVD makes ALD films a tractable solution for scale-up paths toward high-volume manufacturing for our researchers and industrial clients. This ensures a viable pathway from academia to real economic impact in our region.”
Going Up! Monolithic 3D as an Alternative to CMOS Scaling
By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)
The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as much calculating power as multi-million-dollar supercomputer 10 years ago! But at 28nm, it seems the race is over: Moore’s scaling is facing obstacles – parasitic phenomena, incompressible delays, energy dissipation – that can be overcome with technology, but not in a way that is economically sustainable for everyone. This is where the idea to go 3D comes in: the density and cost dictated by Moore’s Law would be achieved not by 2D shrinking but by going up into the third dimension.
Piling transistors on top of each other in a “3D” configuration is not new. Stacking techniques using through-silicon vias (TSVs) are currently used for CMOS image sensors, MEMS, and now 3DNAND. In these scenarios, the devices themselves are processed on separate wafers, then aligned and bonded. The TSVs are essentially copper columns added to connect the top and bottom devices. While beneficial in certain cases, the TSV approach faces its own set of challenges with respect to aligning the transistors, the comparatively wide diameters of the TSVs, the pitch and the overall thickness.
Monolithic 3D (M3D), which takes a very different approach to stacking transistors on top of each other, is one of the most promising alternatives approaches when going 3D. M3D aims at increasing transistor density “sequentially” – meaning within a single process flow, as opposed to the TSV approach, which is applied to die that have already been processed. Staying within the bounds of a single process flow makes M3D much more cost-effective. M3D will enable an increased density of transistors without requiring the downscaling of their individual features. M3D could also provide a gain in performance by reducing the metal wiring delay, thanks to direct contact between transistor levels. From a cost perspective, M3D appears to offer a competitive advantage over equivalent N+1 scaling nodes: the scaling achieved in node N and even N-1 can be leveraged for another generation.
At CEA-Leti in Grenoble (France), one of the world’s most advanced microelectronics R&D centers, CMOS-device teams are exploring various routes to meet increased performance requirements of future semiconductor applications. M3D is a primary focus in the search for alternate routes to scaling, in addition to other disruptive approaches such as steep slope devices, mechanical switches based on NEMS and single electron transistors.
Leti is known for its expertise in the fields needed to demonstrate and take the industry lead in the M3D concept:
- a strong background-related to SOI devices fabrication
- a long history of process developments in molecular bonding of various substrates and materials, essential for creating a high-quality top active layer
- thorough experience in 3D stacking techniques, including design-tool developments, architecture exploration and test-vehicle or full-circuit implementations.
Leti’s M3D program was first launched in 2007. In order to reach the expected performance with an acceptable time to market, M3D must be developed with close, simultaneous attention to applications, design and technology challenges. The success demonstrated since the program launch prompted Qualcomm to partner with Leti in 2014 to explore M3D technology potential for future generations of products.
Leti’s M3D: How it’s done
The M3D concept consists of sequentially processing:
- processing a bottom MOS transistor layer
- processing another MOS transistor layer on top of the bottom one with lithographic alignment between the layers
- positioning metal lines between the two layers to allow connections between both transistor levels.
- encapsulating the inter-metal levels in an oxide layer
- bonding a wafer substrate to the top transistor layer using molecular bonding
- a planarization process.
Using an SOI wafer for the top layer molecular bonding provides higher crystalline quality, greater integration density, and accurate thickness control. CEA-Leti has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.
M3D Advantages
The main advantages of M3D are derived from the sequential fabrication of the various transistor layers on the same wafer. It leads to very high alignment accuracy (3D contact pitch <100nm using lithography tools adapted to 14nm production), uses high-density interconnects, and surpasses 3D-TSV performance at a competitive cost. The inter-metal levels also facilitate design partitioning and architecture exploration.
Leti’s M3D approach is of particularly high value for those products that do not really benefit from scaling, especially when cost constraints are stringent. Different design simulations estimate a gain of one-node performance without scaling constraints. Once the remaining challenges are overcome, potential applications range from heterogeneous stacks (imagers, MEMS on logic) to advanced memory structures, advanced processors, programmable logic and various SOCs. All those products would benefit greatly from the added value provided by M3D:
- High-circuit density provided by stacking active layers in 3D at minimum-contact pitch level
- Better power dissipation (greater absorption across inter-metal levels surface)
- Increased speed/power performance trade-off by reducing high-resistivity metal wiring length.
- Competitive cost advantage by re-using a given node process scheme without requiring additional/new steps to achieve performance gains.
PDK & Model Availability
In addition to the M3D technology process flow development, CEA-Leti is also proposing a Predictive Design Kit (PDK) that provides a primitive M3D product design environment for integrated modeling, simulation, visualization and communication. It also includes validation tools that product designers need to benchmark M3D and explore new architecture concepts. The first M3D PDK version available from CEA-Leti will permit partners to get a first knowledge of the M3D technology, so they can run initial performance assessments regarding density, speed, power and cost.
Future Development
Part of CEA-Leti’s mission is to develop technologies that are ready to transfer to industry, supporting customers in both developing knowledge and implementation on the manufacturing floor. In the case of M3D, CEA-Leti is beginning to build a full ecosystem of partners to enable the rapid industrialization of this technology. Qualcomm, a world leader in wireless technologies, joined CEA-Leti in its M3D R&D program in 2014 and has committed resources to assess the feasibility of the concept.
To expand the momentum around M3D, while validating design-and-process assumptions and expected performance through prototyping demonstrators, the ecosystem should also involve a major foundry. CEA-Leti also plans to include additional members of the semiconductor business value chain (device modeling, EDA, process tooling, test, etc.) to form a complete M3D ecosystem, and make M3D a competitive technology for industrial transfer.
In the short term, CEA-Leti is looking for interested companies to engage in an R&D program aimed at validating proof of concept of an M3D integration process flow and its related libraries for advanced CMOS nodes.
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Publications reference:
- P.Batude et al – 3D Monolithic Integration, IEEE 2011
- P.Batude et al – 3-D Sequential Integration: a Key Enabling Technology for Heterogeneous Co-Integration of New function with CMOS, IEEE Journal on Emerging and selected topics in Circuits & Systems, 2012
- S.Bobba et al – CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits, IEEE 2011
- O. Turkyilmaz et al – 3D FPGA using high-density interconnect Monolithic Integration, DATE 2014