FD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we […]
Tag: 3D
Two additions to Altatech equipment lines: 10x faster ultra-thin film deposition; Doppler nano-defect inspection captures true sizing and positioning
Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies […]
SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications
ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. […]
Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)
(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]
Engaging Kleinman (ex-GF/Xilinx) piece on LinkedIn Advocates for 28nm FD-SOI
A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI. Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), […]
SST article details Leti’s Monolithic 3D presentation at Semicon West ’14
An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for […]
Leti’s Monolithic 3D Highlighted in IEEE Spectrum
An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to […]
2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May
IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines). Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]
U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials
The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates […]
Going Up! Monolithic 3D as an Alternative to CMOS Scaling
By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti) The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]