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ISSCC 2011

Website: http://isscc.org
20-24 February 2011, San Francisco, CA

ISSCC – the International Solid-State Circuits Conference – is the flagship conference of the Solid-State Circuits Society. It is widely considered the premier forum for presenting advances in solid-state circuits and systems-on-a-chip.

Here is a round-up of this year’s major SOI-based papers.

Session 4: Enterprise Processors & Components

#4.1:  A 5.2Ghz Microprocessor Chip for the IBM zEnterpriseTM System

J. Warnock, Y. Chan, W. Huott, S. Carey, M. Fee, H. Wen, M. Saccamango, F. Malgioglio, P. Meaney, D. Plass, Y-H. Chan, M. Mayo, G. Mayer, L. Sigal, D. Rude, R. Averill, M. Wood, T. Strach, H. Smith, B. Curran, E. Schwarz, L. Eisen, D. Malone, S. Weitzel, P-K. Mak, T. McPherson, C. Webb (IBM)

With this paper, IBM demonstrated the first commercial processor breaking the 5GHz speed  barrier.  The microprocessor chip for the IBM zEnterprise 196 system, it is implemented in 45nm SOI. It contains 4 processor cores running at 5.2GHz, and includes an on-chip high-speed 24MB shared DRAM L3 cache. The IBM team used a comprehensive design approach combining detailed power modeling and reduction techniques, with programmable timing control and a number of high-performance process-technology features in order to achieve this speed breakthrough within the available power envelope.

#4.2: Dynamic Hit Logic With Embedded 8Kb SRAM in 45nm SOI for the zEnterpriseTM Processor

A. R. Pelella, Y. H. Chan, B. Balakrishnan, P. Patel, D. Rodko, R. E. Serton (IBM)

This paper describes dynamic hit logic with an embedded 8Kbit SRAM. The 14b hit logic uses a search-for-a-hit scheme with programmable launch and reset clocks. Array BIST provides both the hit logic and SRAM with full at-speed test coverage. The SRAM (1R/1W) uses 45nm SOI 6T cell with domino hierarchical dual-read bitlines.

#4.5:  Design Solutions for the Bulldozer 32nm SOI 2-core Processor Module in an 8-Core CPU

T. Fischer, S. Arekapudi, E. Busta, C. Dietz, M. Golden, S. Hilker, A. Horiuchi, K. A. Hurd, D. Johnson, H. McIntyre, S. Naffziger, J. Vinh, J. White, K. Wilcox (AMD)

This paper describes the new “Bulldozer” 2-core CPU module that contains 213M transistors in an11-metal layer 32nm high-k metal-gate SOI CMOS process. In addition to the micro-architecture improvements, the components, such as the L1 and L2 caches, the integer unit and the Floating Point unit, are designed to achieve higher frequency, lower power consumption, and lower gate counts per cycle than the 45nm AMD core while maintaining IPC (Instructions per Cycles). It achieves over 3.5GHz in an area (including 2MB L2 cache) of 30.9mm2.

#4.6:  40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core

M. Golden, S. Arekapudi, J. Vinh (AMD)

This paper presents a 40-instruction out-of-order scheduler that issues four operations per cycle and supports single-cycle operation wakeup. The integer execution unit supports single-cycle bypass between four functional units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom design. Architectural choices minimize power consumption.


Session 8: Wireline Architectures and Circuits for Next Generation Wireline Transceivers

#8.8: A 14Gb/s High-Swing Thin-Oxide Device SST TX in 45nm CMOS SOI

C. Menolfi, T. Toifl, M. Rueegg, M. Braendli, P. Buchmann, M. Kossel, T. Morf (IBM, Miromico)

The IBM/Zurich R&D team presented a 14Gb/s high-swing source-series-terminated (SST) TX that features up to twice the signaling amplitude of a conventional SST design. The 4-tap FFE TX is based on a high-voltage, thin-oxide device SST output driver stage whose pull-up and pull-down switches are driven from separate, split supply pre-drivers. Implemented in 45nm CMOS SOI, the circuit consumes 85.5mW at 14Gb/s from a nominal supply of 1V and an output driver supply of 2V.


Session 12: Design In Emerging Technologies

#12.4:  A 3.9ns 8.9mW 4×4 Silicon Photonic Switch Hybrid Integrated with CMOS Driver

A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, M. Yang, F. Doany, S. Assefa, C. Jahnes, J. Kash, Y. Vlasov (IBM)

A monolithic 4×4 silicon photonic router, composed of 6 2×2 2mW 3.9ns 300×50µm2 Mach-Zehnder interferometer switches, is flip-chip bonded with a custom 90nm bulk CMOS driver, routing 3×40Gb/s WDM data with BER <10-12, less than -10dB cross-talk and 7dB loss. The size of the micro-assembly is 1×2×2mm3.


Session 14:  High-Performance Embedded Memory

#14.1: A 64Mb SRAM in 32nm High-k Metal-Gate SOI Technology with 0.7v Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

H. Pilo, I. Arsovski1, K. Batson, G. Braceras, J. Gabric, R. Houle, S. Lamphier, F. Pavlik, A. Seferagic, L-Y. Chen, S-B. Ko, C. Radens (IBM)

This paper described the first 32nm embedded SRAM SOI implementation that enables low-power operation down to 0.7V.  The SRAM features a 0.154µm2 bitcell. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline regulation scheme that reduces charge injection into the bitcell. Enhancements to the write path include an increase of 40% of bitline boost voltage. Finally, a bitcell-tracking delay circuit improves both performance and yield across the process space.

#14.2: A 4R2W Register File for a 2.3Ghz Wire-Speed PowerTM Processor With Double-Pumped Write Operation

G. S. Ditlow, R. K. Montoye, S. N. Storino, S. M. Dance, S. Ehrenreich, B. M. Fleischer, T. W. Fox, K. M. Holmes, J. Mihara, Y. Nakamura, S. Onishi, R. Shearer, D. Wendel, L. Chang (IBM)

IBM introduces architectural techniques to significantly improve the area, power, and performance of multi-ported register file arrays. A 144×78b macro for a 45nm SOI-CMOS 2.3GHz POWER™ processor is presented with double-pumped write ports that are operated twice in a single cycle and replicated read ports that are combined from duplicate data copies. A compact 2R1W memory cell is thus leveraged to perform a 4R2W function with near 2× area and read power reduction, low 190ps read latency, and fast error correction. The macro operates at up to 2.76GHz at a supply voltage of 0.9V.

#14.3: An 8MB Level-3 Cache in 32nm SOI With Column-Select Aliasing

D. Weiss, M. Dreesen, M. Ciraula, C. Henrion, C. Helt, R. Freese, T. Miles, A. Karegar, R. Schreiber, B. Schneller, J. Wuu (AMD)

This paper presents the design of the 8MB level-3 cache in 32nm SOI-CMOS for AMD’s next-generation Bulldozer architecture that operates above 2.4GHz at 1.1V. Area efficiency is improved by the use of a column-select aliasing technique, in which column select wires are shared between odd and even pairs for reads and writes, while leakage power is minimized by supply gating and floating bitlines. An efficient redundancy scheme is also implemented using centralized redundancy blocks instead of storing all redundant data in the data macro itself.


Session 19:  Energy-Efficient Digital Low-Power Digital Techniques

#19.3: Comparison of 65nm LP Bulk and LP PD-SOI With Adaptive Power Gate Body Bias for an LDPC Codec

J. Le Coz, P. Flatresse, S. Engels, A. Valentian, M. Belleville, C. Raynaud, D. Croain, P. Urard (STMicroelectronics, CEA-LETI-MINATEC)

This paper compares a 65nm LP PD-SOI technology combined with an enhanced power gate device utilizing automatic adaptive body bias, to a standard LP CMOS bulk implementation, demonstrating an 802.11n LDPC codec. The authors show how a low resistivity produced with forward body bias of the power switch, combined with PD-SOI can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.


Session 25:  Wireline CDRs and Equalization Techniques

#25.6: A 15Gb/s 0.5mw/Gb/s 2-Tap DFE Receiver With Far-End Crosstalk Cancellation

M. Honarvar Nazari, A. Emami-Neyestanak (CalTech)

In this paper, a 2-tap DFE receiver is implemented in a 45nm SOI technology. High data rate and low power dissipation is achieved using a switched-capacitor S/H/summer front-end, which enables FEXT cancellation with 33µW/Gb/s/lane power overhead. It equalizes 15Gb/s data over a link with >14dB loss and dissipates 7.5mW from a 1.2V supply.

20-24 February 2011, San Francisco, CA

AMD’s New Fusion APU’s on 32nm SOI

The AMD PR folks are calling their new Fusion APUs the era of  “Personal Supercomputing”  – and its flagships are on 32nm SOI   We’ve been hearing about these revolutionary chips for years now – the “Fusion” of graphics chips – GPUs – and CPUs on a single piece of silicon, which they’re referring to as an APU – an “Accelerated Processing Unit”.

Launched last week at CES in Las Vegas, the SOI-based “mainstream platform” is primarily intended for performance and mainstream notebooks and mainstream desktops. First up is the 32nm die A-Series “Llano” APU, which includes up to four x86 cores and a DirectX 11-capable discrete-level GPU.  It’s scheduled to ship in the first half of 2011 and appear in products mid-year.

Now, with a bit of detective work, we can sort out the SOI-based APU roadmap that AMD announced at its Financial Analyst’s Day in November 2010.

AMD divides its roadmap into “Notebooks”, “Desktop” and “Server”. Here’s what to look for on 32nm SOI.

Notebooks – CPU/APU Roadmap:

  • “Llano” Fusion APU – has 2-4 “Stars” CPU cores  – comes out this year (the 45 to 32nm SOI port of “Stars”, which is based on the existing architecture, was detailed at ISSCC last year)
  • Next year (2012), they’ll add the “Trinity” Fusion APU, based on 2-4 all-new next-gen “Bulldozer” CPU cores

Desktop CPU/APU Roadmap:

  • This year, look for the “Zambezi” CPU, with 4-8 Bulldozer CPU cores
  • and the “Llano” Fusion APU with 2-4 Stars CPU cores
  • Next year, it’s the “Komodo” CPU with 8 Bulldozer CPU cores,
  • and the “Trinity” Fusion APU with 2-4 next-gen Bulldozer cores

Server CPU Roadmap:

  • This year, it’s the “Interlagos” CPU with 8/12/16 Bulldozer CPU cores
  • and the “Valencia” CPU with 6/8 Bulldozer CPU cores
  • Then next year, it’s the “Terramar” CPU with up to 20 (!!) next-gen Bulldozer CPU cores,
  • and “Sepang” with up to 10 next-gen Bulldozer CPU cores.

GlobalFoundries is of course the fab – debuting 32nm SOI with high-k/metal-gate (HK/MG).  Here’s what CEO Doug Grose showed financial analyst’s at the end of 2009 (yes, so you can tell any doubters that GloFo was already showing great HK/MG 32nm SOI over a year ago!):

And here’s what Chekib Akrout, senior vice president and general manager, AMD Technology Development, showed the financial analysts in November 2010:

Very cool stuff.  What do you think?  Will it find its way into your products or onto your desktop this year?

Then of course there’s all these changes in the upper echelons of AMD management that transpired this week, plus the Intel/nVidia settlement.  What does your crystal ball say about all that? Leave a comment and let us know.

(All images courtesy of AMD.)

In addition to announcements of extensions of its existing platforms, AMD issued its SOI roadmap news (by codename)

In addition to announcements of extensions of its existing platforms, AMD issued its SOI roadmap news (by codename).

Plans for 2010 include:
• “Danube” – mainstream notebook platform featuring the first AMD mobile quad-core processors;
• “Nile” –  ultrathin notebook platform.
• “San Marino” and “Maranello” – 8- and 12-core processors for the volume server market with unprecedented performance-per-watt.
• “Leo” –  next-generation enthusiast-class desktop PC platform with the industry’s first six-core desktop CPU.

Plans for 2011 include:
• “Bulldozer” – a new x86 CPU core for linking with GPUs in single-chip Accelerated Processing Unit (APU) configurations.
• “Llano” – for mainstream notebooks and desktops, this APU will be the first in a family of next-generation designs that combine the power of the CPU and GPU onto a single piece of silicon.
• “Zambezi” – an enthusiast desktop processor with up to eight cores, featuring the first “Bulldozer” core.

New 45nm chips from AMD

  • New 45nm chips from AMD (which builds all its 64-bit microprocessors on SOI):
    Athlon™ II X2 250 processor for mainstream consumers and the Phenom™ II X2 550 Black Edition processor, the first ever dual-core AMD Phenom II CPU.
    • the Six-Core AMD Opteron™ processor family, to address rising demand for increased performance balanced by greater power-efficiency for cloud computing and web serving environments.

New from AMD

  • New from AMD (which builds all its 64-bit microprocessors on SOI):

    • the four-core Phenom™ II X4 (up to 3GHz) and Black Edition (3.2GHz) and the triple-core Phenom™ II X3 (up to 2.8GHz) on 45nm SOI, which are at the heart of the “Dragon” platform (with headroom for overclocking), targeting demanding gaming and consumer applications;

    • the Athlon™ Neo processor for ultra-thin notebook designs;

    • the Athlon™ X2 7850 Black Edition processor for PC users seeking a full-featured product with best-in-class price-performance;

    • the 40W ACP AMD Opteron™ EE processor, full-featured energy miser offering 13% power savings, and targeting very dense data center environments;

    • the six-core AMD Opteron processor code-named “Istanbul” is slated for delivery in June of this year, months ahead of schedule.

Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More

From AMD

From AMD (which builds all its 64-bit microprocessors on SOI):
• The new 45nm Quad-Core AMD Opteron™ (“Shanghai”) pushes performance up 35% and power consumption down 35%.
• The newly announced Foundry Company will be in the IBM technology development alliance for both SOI and bulk technology.

IBM

  • IBM:

• IBM has licensed the multi-protocol SerDes cell from Rambus for high-performance and low-power 45nm SOI.

• For the most challenging arithmetic operations, IBM’s new PowerXCell™ 8i (65nm SOI) offers five-times the speed of the original Cell/B.E. processor.

“Roadrunner” (Courtesy: IBM)

• The “Roadrunner” supercomputer at Los Alamos shot to #1 on the TOP500™ Supercomputer list with sustained performance of 1.02 petaflops (1.02 quadrillion calculations per second). Its 12,240 SOI-based IBM PowerXCell 8i processors crunch the numbers, while 6,562 SOI-based AMD Opteron™ Dual-Core processors handle the basic computing

Mentor Graphics advanced lithography tools, which are accelerated with an SOI-based Cell/B.E. cluster from Mercury Computer Systems, are now IBM qualified for production of 45nm Cells.

AMD (which builds all its 64-bit microprocessors on SOI)

  • AMD (which builds all its 64-bit microprocessors on SOI):

• An AMD spokesperson has confirmed that the first Fusion (CPU/GPU) chip, designed by a worldwide team, is on SOI and will be manufactured in Dresden.

• The new Turion X2 Ultra Dual-Core Mobile doubled notebook
design wins.

Recent Conference Proceedings

May 2008, Hsinchu, Taiwan

Defect Delineation and Characterization in SiGe, Ge and other Semiconductor-on-insulator Structures. (Invited) Alexandra Abbadie, F. Allibert, F. Brunier (Soitec)

Performance and Scaling of cMOSFETs on Ultra-Thin Strained SOI. (Invited) Francois Andrieu, V. Barrel, T. Poiroux, O. Faynot, S. Deleonibus (CEA-LETI Minatec)

Spectral Responsivity of Fast Ge Photodetectors on SOI. Mathias Kaschel, M. Kaschel, M. Oehme, O. Kirfel, J. Lupaca-Schomber, E. Kasper (Universitat Stuttgart)

May 2008, Phoenix, Arizona, USA

Material Aspects and Challenges for SOI FinFET Integration (E1 636, Invited)

M. J. Van Dal, G. Vellianitis, R. Duffy, B. Pawlak, K. Lai, A. Hikavyy, N. Collaert, M. Jurczak and R. Lander (NXP, TSMC, IMEC)
This paper elaborates on the key material aspects of front-end-of-line SOI trigate FinFET integration with high fin aspect ratio. It shows that the formation of low resistive contacts including extension, selective epitaxial growth (SEG) on the fin source/drain areas, optimized source/drain implants and silicidation conditions are paramount to achieve low access resistance and high drive currents.

Ge Enrichment Technique on SiGe/SOI Mesa Islands: a Localized GeOI Structures Fabrication Method (E1 637)
B. Vincent, J. Damlencourt, Y. Morand, D. Rouchon and M. Mermoux (CEA, STMicroelectronics, INPG)
The paper says that to be advantageous, GeOI structures need to be confined within pMOSFET channels or limited to active zones available for pMOSFETs. It proposes for the first time an identification of all mechanisms induced in this technique, limitations highlights and improvements proposals. The local Ge enrichment technique consists of a selective Si oxidation of a SiGe/SOI mesa island previously etched to the BOX. The authors propose a review of all mechanisms involved in the local Ge enrichment techniques, and conclude that strain engineering is necessary on initial structures to get final homogeneous Ge enriched mesa islands.

Hole Mobility Behavior in Strained SiGeon-SOI p-MOSFETs (E1 656)
T. Shim, S. Kim, J. Baek, H. Lee, G. Lee, K. Kim, W. Cho and J. Park (Nano-SOI Process Lab, Hanyang University, Kwangwoon University, South Korea)
This study investigates the hole mobility behavior in a compressive strained SiGe layer grown on SOI, depending on effective electric fields, Eeff , by varying Ge concentrations.

Silicides for 32nm and Beyond (E673)
P. R. Besser, C. Murray and C. Lavoie (AMD, IBM)
This presentation shows the silicide engineering advantages of incorporating alloying elements with Ni, and highlights the manufacturing challenges of NiSi, improving morphological stability enhancing the device performance and yield of high-performance SOI technologies for microprocessors, for example.

May 2008, Strasbourg, France

Evolution of end-of-range defects in silicon-on-insulator substrates.
From the EU IST ATOMICS project team: P.F. Fazzini, F. Cristiano, C. Dupré, S. Paul, T. Ernst, H. Kheyrandish, K.K. Bourdelle, and W. Lerch. (Fraunhofer, CNRS, CSMA, Mattson, ST, Synopsys, U.Newcastle and Soitec).

June 2008, Grenoble, France

Low-Voltage Scaling Limitations of Nano-Scale CMOS LSIs (tutorial).
This tutorial describes low-voltage scaling limitations of nano-scale CMOS LSIs , focusing on specific circuit blocks such as logic gates, SRAM cells, and DRAM sense amplifiers. Possible solutions to drastically reduce Vmin are presented and evaluated. They are repair techniques, new MOSFETs (such as metal-gate bulk and metal-gate FD-SOI), and low-VT dynamic circuits. Kiyoo Itoh (Hitachi).

Fully Depleted SOI devices for Low Power technologies (invited)
O.Faynot (CEA)

CMOS SOI technology for WPAN Application to 60Ghz LNAs (invited)
A. Siligaris, C. Mounet, B. Reig, P. Vincent, A. Michel (CEA-Leti, ANSOFT).

SRAM Memory Cell Leakage Reduction Design Techniques in 65nm Low Power PD-SOI CMOS
Olivier Thomas, Marc Belleville, Richard Ferrant; (CEA, Minatec, ST)

An SOI-based Self-aligned Quasi-SOI MOSFET with Π-shaped Semiconductor Conductive Layer
Yi-Chuen Eng, Jyi-Tsong Lin, Shiang-Shi Kang (National Sun Yat-Sen University, Taiwan)

SOI Chip Design and Charging Damage (invited)
Terence B. Hook (IBM)

June 2008, Monterey, CA, USA

Fracture Mechanism in Hydrogen Implanted Germanium
F. Mazen,; A.Tauzin, L. Sanchez, F. Chieux, C.Deguet, , France; E. Augendre, C, France; C. Richtarch,; T. Akatsu,; L. Clavel, (CEA-Leti-Minatec, Soitec)

Layer Transfer with Implant induced Defects: A Path to Advanced Engineered Substrates (invited)
K.K. Bourdelle (Soitec)

Automotive SOI-BCD Technology Using Bonded Wafers (invited)
H. Himi, S. Fujino (Denso)

Comparison of Dopant Activation and Diffusion for Varying B Doses and PAI Conditions in Preamorphized Si and SOI
K.J. Kirkby (University of Surrey, UK)

A Comparative Study of Interaction of the End of Range (EOR) Defect Band with the Upper Buried Oxide (BOX) Interface for B and BF2 Implants in SOI and Bulk Si With and Without a Pre-amorphising Implant
A. J. Smith, J.J. Hamilton, B. Colombeau, R.P. Webb, R.M. Gwilliam, J. Sharp, K.J. Kirkby, M. Kah, (U. Surrey, UK; Chartered)

June 2008, Honolulu, Hawaii, USA

Technology Session 2 — FinFET and Multi-Gate MOSFETs
Novel Integration Process And Performances Analysis Of Low Standby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) On SOI With Metal / High-K Gate Stack
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Barral, V. Maffini-Alvaro, F. Andrieu, C. Vizioz, Y. Campidelli, P. Gautier, J.-M. Hartmann, R. Kies, V. Delaye, F. Aussenac, T. Poiroux, P. Coronel, A. Souifi, T. Skotnicki, S. Deleonibus (CEA-Leti-Minatec, STMicroelectronics, INL-INSA)
This paper reports on work on SOI with a Metal / high-K Gate stack leading to the best ION/IOFF ratios ever reported: 1.4×108 (0.8×108) for 50nm n- (p-) MCFETs. The authors show, based on specifically developed integration process, characterization methods and analytical modeling, how this performance is obtained thanks to specific 3D MCFET features, in particular, transport properties, saturation regime and electrostatic behavior.

Technology Session 9 – Highlights
A Scaled Floating Body Cell (FBC) Memory with High-k +Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond
I. Ban, U. Avci, D. Kencke, P. Chang (Intel)
A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-microAmp sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at the 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Technology Session 17 – Advanced SOI
Smallest Vth Variability Achieved by Intrinsic Silicon on Thin BOX (SOTB) CMOS with Single Metal Gate
Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, S. Kimura (Hitachi, Renesas)
“Silicon on thin BOX” (SOTB) achieved the smallest Vth variability. The Pelgrom coefficients were 1.8 (NMOS) and 1.5 (PMOS), even in the case of relatively thick EOT of 1.9 nm. In this SOTB, multi-Vth control and suppression of short-channel effects were performed by adjusting the impurity concentration beneath the BOX keeping the channel almost intrinsic. The scalability of the SOTB is shown.

Selenium Co-implantation and Segregation as a New Contact Technology for Nanoscale SOI N-FETs Featuring NiSi:C Formed on Silicon-Carbon (Si:C) Source/Drain Stressors
H.-S. Wong, F.-Y. Liu, K.-W. Ang, S.-M. Koh, A.T.-Y. Koh, T.-Y. Liow, R.T.-P. Lee, A.E.-J. Lim, W.-W. Fang, M. Zhu, L. Chan, N. Balasubramaniam, G. Samudra, Y.-C. Yeo (National University of Singapore, Institute of Microelectronics, Singapore)
The paper reports a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height ФBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low ФBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with and without Se segregation. When integrated in nanoscale SOI n-FETs with Ni-silicided Si:C S/D, the new Se-segregation contact technology achieves 36% reduction in total series resistance and 32% ION enhancement. Linear transconductance GML in also shows large enhancement in the sample with Se-segregated contacts.

Mobility Of Strained And Unstrained Short Channel FD-SOI Mosfets: New Insight By Magnetoresistance
M. Casse, F. Rochette, N. Bhouri, F. Andrieu, D.K. Maude, M. Mouis, G. Reimbold, F. Boulanger, (CEA-Leti-Minatec, CNRS-GHMFL, IMEP CNRS/INPG/UJF)
Electron mobility in strained and unstrained FD-SOI MOSFETs is deeply investigated in linear regime by careful magnetoresistance measurements down to 40nm gate length and 20K. This method differs from standard ones because: it does not require any data on the short channel gate capacitance and gate length; it is more accurate at low inversion charge; the temperature dependence of the Coulomb Scattering (CS) limited mobility is higher. Additional mobility scattering has been confirmed for short channel nMOS, and unambiguously identified as CS. A 50% mobility gain for strained Si MOSFETs is still observable even in this dominant CS regime.

On Implementation of Embedded Phosphorus-doped SiC Stressors in SOI nMOSFETs
Z. Ren, G. Pei, J. Li, B.F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J.W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, R. Pal, I. Lauer, D-G. Park, D. Sadana (IBM, AMD)
The paper reports a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. The authors identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the Stress Memory Technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

Ten years after – Has SOI finally arrived?
(Technology Rump Session) A similar panel held 10 years ago concluded that SOI has a performance advantage over bulk, but cost would be its main barrier for wide adoption. The 2008 panel asks if anything has changed and will it change in the next decade? Will SOI penetrate more market segments or disappear? Does further technology scaling require the migration to fully-depleted SOI? Panelists: M. Bohr, Intel; R. Mahnkopf, Infineon; G. Shahidi, IBM; C. Mazure, Soitec; E. Suzuki, AIST; D. Scott, TSMC; A. Kameyama, Toshiba; M. Usami, Hitachi.