Tag Archive analog

ByAdministrator

Yes, 28nm FD-SOI Silicon Is Running (Samsung Interview, Part 1 of 3)

(New)Kelvin Low Portrait 2015

Kelvin Low, senior director of marketing for Samsung Foundry

Axel_Fischer_Samsung_28FDSOI_sm

Axel Fischer, director of Samsung System LSI business in Europe

ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.

~ ~ ~

ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?

Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.

What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.

Samsung_28FDSOI_PDKS_12Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship

KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.

We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.

ASN: Do you have other customers lined up?

KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.

ASN: What about technology readiness and maturity?

KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.

Samsung_28FDSOI_process_costThis slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.

ASN: When will we see the first high-volume FD-SOI chips? Next year?

KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.

AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.

KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.

[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]

Samsung_28FDSOI_wafersAF: ST is our first partner for high-volume production. We started working together very early, so they have a time-to-market advantage.

KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.

~ ~ ~

This is the first installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. Part 2 will cover design considerations, and Part 3 will look at the ecosystem.

ByGianni PRATA

FD-SOI makes analog designers happy (NewElectronics)

A recent NewElectronics article entitled ST’s FD-SOI transistor is set to give analogue designers a new knob to tune parameters, explores the many reasons that FD-SOI makes designers happy – even the analog folks. Editor Graham Pitcher talked to analog designer Andreia Cathelin, a senior member of STMicroelectronics’ technical staff. Among plenty of other things, she noted that with FD-SOI, “…transistors can offer the same analogue gain as they did at 130nm, but with the advantages of a 28nm channel.”(Read the full article here.)

It also helps simplify tuning in that you can change one parameter (linearity, noise, power consumption) without the change affecting the other parameters, she notes. For digital, she especially likes that FD-SOI can be biased up to +2V, compared to about 0.3V for bulk.

She concludes, ” “Analogue designers are happier; the transistor is back to offering good intrinsic performance and there is a ‘knob’ outside of the signal path. But if designers want to get the most out of FD-SOI, they will need to think about what they can do with that ‘knob’.”

A recommended read.

ByAdministrator

First SOI wafers based on Smart Cut tech produced in China, target strong 200mm SOI demand in smart power, RF, automotive

Shanghai-based Simgui has produced the company’s first 200mm SOI wafers based on Soitec‘s Smart CutTM manufacturing technology (read the press release here). Samples will be going to customers in the coming weeks for qualification, with high-volume ramp planned for early 2016. Simgui will be selling the wafers directly to its own customers in China, and manufacturing on an OEM basis for Soitec customers worldwide. This includes manufacturing Soitec’s fabulously successful RFeSI90 substrates for LTE-A, 5G and Gigabit Wi-Fi in smartphones and other devices (read about those here), substantially increasing worldwide capacity to meet the recent rapid rise in demand.

1stSmartCutSimgui3

Simgui’s first 200mm SOI wafer manufactured using Soitec’s Smart Cut technology. (Courtesy: Simgui)

While overall worldwide 200mm wafer demand (including bulk and epi) has slipped a bit over the last year (they’re now accounting for a little over a quarter of all wafer sales), demand is increasing for certain types of 200mm SOI wafers. What’s driving it? RF and smart power (both of which are seeing big opps in automotive). SOI wafer leader Soitec, for example, is seeing an uptick of 20% in 200mm SOI wafers for smart power for automotive. RF is growing even faster.

The thick and thin of it

What’s different about these 200mm SOI wafers? It’s a question of layer thickness, quality and the manufacturing technology used to make them. Simgui and many others have been producing very “thick” 200mm SOI wafers for years. Traditionally in “thick” SOI (which has been used in things like power, aerospace, automotive, MEMS and sensors for decades), the top silicon might be up to anywhere from 2 µm to 300 µm thick, with an insulating box layer in the range of 3 µm (sometimes much more). But new apps in smart power and RF, for example, need a very high quality top silicon layer that might be as thin as 0.145µm for power*, or under 0.1µm for RF. The insulating layer also needs to be far thinner, and the bottom supporting layer also has to fulfill specific, advanced parameters.

(Bear in mind that these wafers for RF and smart power are still relatively thick compared to what you need for FD-SOI, for example, which is considered “ultra-thin”, and has ultra-uniform top silicon with a thickness in the range of 10-20 nm (0.01 – 0.02µm).)

SOI_thickness_by_appV8

This graphic explains which SOI wafers are used for which applications, correlating top silicon and insulating buried oxide layer thicknesses.

There are several different manufacturing approaches to fabricating SOI wafers. To make the SOI wafers needed for new markets in smart power and RF, Simgui has opted to use Soitec’s Smart Cut technology (which is well-explained here). Smart Cut’s especially good for producing very high-quality wafers, with a thin and very uniform top layer of silicon and a thin layer of insulating buried oxide (BOx).

The new deal

Simgui is a high-tech company in Shanghai focused on supplying SOI wafers and providing foundry services for epi wafers. It was spun off from the Shanghai Institute of Microsystem and Information Technology (SIMIT) within the Chinese Academy of Sciences (CAS) and now is a joint venture with a group of investors from Silicon Valley. Both its SOI and epi businesses are growing dramatically.

With a surge in demand for leading-edge thick 200mm SOI wafers, Simgui partnered with Soitec, the industry’s SOI wafer leader, back in May 2014 (see that press release here).

SimguiFab3

Simgui’s Fab-3 in Shanghai, where the company is manufacturing 200mm SOI wafers for power & RF using Soitec’s Smart Cut technology.

The May 2014 deal was a licensing and technology transfer agreement under which Simgui would manufacture Soitec’s 200-mm SOI wafers using Soitec’s proprietary Smart Cut™ technology. The news now is that it’s actually happened. Simgui has established a high-volume SOI manufacturing line to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide in the growing RF and power markets. Beyond this initial cooperation, the two companies are expanding their collaborative efforts in the future to take advantage of their synergies.

China markets and beyond

Roughly a third of the fabs in China are 200mm (see SEMI’s map below). As recently noted by IC Insights, “Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.”

ChinaMapSEMI2015

Current map of fabs by wafer diameter in China (as of April, 2015, Courtesy: SEMI)

The Soitec-Simgui partnership addresses two key areas: 1. China’s growing demand and 2. the need for an increase in worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. It’s also seen as a key element in establishing an SOI ecosystem in China.

Dr. Xi Wang, chairman of the board of directors of Simgui, notes that, “China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry.”

It’s also good news for Soitec’s 200mm SOI customers. “We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.

Which explains why the two companies see it as a win-win situation.

ByAdministrator

It’s Official! GlobalFoundries Launches 22FDX: 22nm FD-SOI in 4 flavors

With much fanfare, GlobalFoundries has officially announced its 22nm FD-SOI offering. Dubbed “22FDX™”, GF says the platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar, targeting mainstream mobile, IoT, RF connectivity and networking markets.

Asked by EETimes why FD-SOI here and now, GF’s CEO Sanjay Jha responded, “The mass market is at 28nm/22nm. Really it is leading-edge pure digital that is the niche.” (Read Peter Clarke’s full piece here.)

And so a new paradigm is born.

With FinFETs relegated to the leading-edge-pure-digital niche, GF says FD-SOI provides the best path for cost-sensitive applications (which is everything else, right?!). Their pitch: 22FDX offers the industry’s lowest operating voltage (0.4 volt), enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. Plus it delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

It’s been three years since ST announced (in June 2012) that GF would be providing high-volume sourcing for FD-SOI, but you never saw it on GF’s website — til now. As of 13 July 2015, it’s there in a big way. Today, you can finally go to the GF website and see the headline on the homepage, or find out all about the offer on dedicated tech solution pages (click here to check it out yourself).

GF_FDSOI_website

A snapshot of the GlobalFoundries website page for the new 22nm FD-SOI platform.

GF_FDSOI_apps

Target apps for 22FDX (Courtesy: GlobalFoundries)

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Jha, who was on hand for the big event in Dresden, Germany. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”

And of course it’s good new for the folks at GF’s Fab 1 in Dresden, in the heart of Germany’s “Silicon Saxony” region. GF’s invested another $250 million for technology development and initial 22FDX capacity there (that’s on top of the >$5 billion they’ve invested there since 2009). Further investments to support additional customer demand are planned, plus partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering.

If you read the ASN coverage of the FD-SOI Workshop during LetiDays a few weeks ago, you saw that GF’s 22nm FD-SOI has a 14nm front end and 28nm back end (read it here if you missed it before). At LetiDays, they also talked about body-bias “generators”. In the 22FDX press release they’re referring to it as “…software-control of transistor characteristics to achieve real time tradeoff between static power, dynamic power and performance.”

GF_FDSOI_FBBgraphic

GF slide from 22FDX launch shows the power of forward body-bias (Courtesy: GlobalFoundries)

4 Flavors

Here are the offerings in the 22FDX platform, each one targeting a specific area of applications.

22FD-ulp: ulp aka ultra-low power is an alternative to FinFET for the mainstream and low-cost smartphone market. With body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET, says GF. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.

22FD-uhp: uhp aka ultra-high performance – this offers networking applications with analog integration the capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.

22FD-ull: ull aka ultra-low leakage targets wearables and IoT. It delivers the same capabilities of 22FD-ulp, while reducing static leakage to as low as 1pA/μm (pA = picoamp = one million millionth (10-12) of an amp, folks). This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.

GF_FDSOI_platform

Slide shown during the 22FDX launch summarizes GF’s four FD-SOI flavors. (Courtesy: GlobalFoundries)

22FD-rfa: rfa aka integrated RF and analog. It delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.

GF says they’ve been working closely with key customers and ecosystem partners to enable optimized design methodology and a full suite of foundational and complex IP. Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.

What Customers and Partners are saying

ST: “GLOBALFOUNDRIES’ FDX platform, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum of this technology by expanding the ecosystem and assuring a source of high-volume supply,” said Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”

Freescale: “Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino, vice president of applications processors and advanced technology adoption for Freescale’s MCU group. “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”

ARM: “The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the IP ecosystem needed for customers to benefit from the unique value of 22FDX technology.”

Verisilicon: “VeriSilicon has experience designing IoT SoCs in FD-SOI technology and we have demonstrated the benefits of FD-SOI in addressing ultra-low power and low energy applications,” said Wayne Dai, president and CEO of VeriSilicon Holdings Co. Ltd. “We look forward to collaborating with GLOBALFOUNDRIES on their 22FDX offering to deliver power, performance and cost optimized designs for smart phones, smart homes, and smart cars especially for the China market.”

Imagination: “Next-generation connected devices, in markets from wearables and IoT to mobile and consumer, require semiconductor solutions that provide an optimal balance of performance, power and cost,” said Tony King-Smith, EVP Marketing, Imagination Technologies. “The combination of GLOBALFOUNDRIES’ new 22FDX technology with Imagination’s broad portfolio of advanced IP – including PowerVR multimedia, MIPS CPUs and Ensigma communications – will enable more innovation by our mutual customers as they bring differentiated new products to the market.”

IBS: “FD-SOI technology can provide a multi-node, low-cost roadmap for wearable, consumer, multimedia, automotive, and other applications,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ 22FDX offering brings together the best in low-power FD-SOI technology in a low-cost platform that is expected to experience very strong demand.”

Leti: “FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie-Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES’ 22FDX for connected technologies.”

Soitec: “GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology.”

You might also want to check out GF’s 22FDX brochure (click here to download it) and watch their technical webinar: Extending Moore’s Law with FD-SOI Technology.

Choice is a beautiful thing, don’t you agree?

ByAdministrator

Yes! FD-SOI IP Ready for GF, Samsung; Ecosystem Now a Force to Be Reckoned With

The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.

In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.

GF: 22 = 14 + 28

GF_FDSOIenablement_LetiDays15

(Courtesy: GlobalFoundries)

Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).

GF_FDSOI_LetiDays15_phases

Most of the challenges for delivering their 22nm FD-SOI offering have been met, said Gerde Teepe, Design Engineering Director at GF/Dresden.The final phase will be completed by the end of this year. (FD-SOI Workshop, LetiDays 2015)

The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.

IP, IP, IP

The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.

Samsung_FDSOI_design_LetiDays15

(Courtesy: Samsung)

Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.

Synopsys_FDSOI_IP_LetiDays15

Synopsys Senior Director Mike McAweeney explaining their Samsung IP strategy at the LetiDays ’15 FD-SOI Workshop.

This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.

IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.

Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)

Body Biasing Goes Adaptive

New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.

Hot Topic: Analog

Thurmann_analogFDSOI_design_LetiDays15

FD-SOI advantages for analog design include outstanding switch performance, said Boris Thurmann of Stanford. (LetiDays ’15)

In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.

FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.

FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.

Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.

You Gotta Believe

In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.

“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.

ST_Skotnicki_FDSOI_LetiDays15

(Courtesy: STMicroelectronics)

He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.

Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).

And clearly, he’s a man who knows the future.

ByGianni PRATA

GF, NXP, Infineon and more at SOI Workshop During Silicon Saxony Day (Dresden, 7 July 2015)

SiEuropeSOIIC

Silicon Europe (an alliance of Europe’s leading micro- and nanoelectronics clusters) and the SOI Consortium have organized an SOI Workshop on the 7th of July 2015, during the 10th Silicon Saxony Day in Dresden.

Here’s the agenda:

  • Quick Introduction
  • More than Moore Market Analysis and Opportunities (Yole)
  • Power SOI and applications (NXP)
  • Foundry offer (GlobalFoundries)
  • FD-SOI status review (Giorgio Cesana, SOI Consortium)
  • Analog/RF, sensors and MEMS in SOI: demos and performance assessment (Denis Flandre, UCL)
  • Automotive IC needs (Infineon)

The workshop, which runs from 1:30 – 4:30, will be held in English. There is an entry fee (waived for students) for Silicon Saxony Day, but once you’re in, the SOI Workshop is free.

ByAdministrator

X-Fab Interview: SOI Solutions for analog/mixed-signal, high-voltage, high-temperature and MEMS Applications

X-FAB_logo_print_loresWith five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.

Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?

Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.

X-FAB_Tilman.Metzger_lowres

Tilman Metzger, Product Marketing Manager for the X-Fab Group. (Courtesy: X-FAB)

Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.

ASN: When did X-Fab first start offering SOI and why?

TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.

ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?

TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.

Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.

ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?

X-FAB_HQ_ErfurtGermany_lowres

X-FAB headquarters in Erfurt, Germany (Courtesy: X-FAB)

TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.

Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.

ASN: When and why do your customers choose an SOI-based process?

TM: Typically, we see two types of SOI customers:

  1. Those that tried and failed a particular design in a BCD/Bulk technology and hence turned to a SOI solution; and
  2. Those that focus on SOI technology right from the start due to IC or system requirements (or past experience). Some of the challenges of such designs may include:
  • Very high temperature of 175-225°C
  • Resistance to EMI* or stringent EMC and ESD requirements
  • Latch-up concerns
  • Negative voltage swings / inductive loads
  • Stringent noise immunity / cross-talk requirements
  • Low leakage at high temperature
  • Aggressive time-to-market requirements

ASN: Can you expand on the time-to-market (TTM) issue a bit?

TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.

ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?

TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.

ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?

TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..

ASN: Can you tell us more about X-Fab’s SOI offerings?

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X-FAB cleanroom in Kuching, Malaysia, where the company runs their new XT018 SOI process. (Courtesy: X-FAB)

TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)

Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.

XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.

XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.

ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?

MEMSfoundryaward_Xfab

X-FAB MEMS Foundry received the “MEMS Foundry of the Year” award at the Best in MEMS & Sensors Innovation Awards ceremony, as part of the MEMS Industry Group’s 10th annual MEMS Executive Congress® held in Scottsdale, Arizona in November 2014. (Courtesy: X-FAB)

TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.  

For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.

We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.

ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?

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Chips manufactured by X-FAB go into key automotive systems. (Courtesy: X-FAB)

TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.

We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.

We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.

ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?

TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.

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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.

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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge

**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.

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IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

Bacchus Entry

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) will be held in Sonoma Valley, CA 5-8 October 2015. (Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.

Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.

EDS Logo PMS3015_revu_smallThe conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

sponsor-ieeeWhile paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.

Program:

Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.

Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.

There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.

Welcome to Doubletree Hotel Sonoma Wine Country

(Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about Ultra-Low Power.

During the Rump session we will debate about the What does IoT mean for semiconductor technology?

Scope of the conference:

The Committee will review papers submitted by May 18 in the three following focus areas of the conference:

 

Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.

 

Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.

 

3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.

Important dates:

Paper submission deadline: 18 May, 2015

Notification of acceptance: 07 June, 2015

Short course date: 5 October, 2015

Conference date: 5 – 8 October, 2015

More details are available on the S3S website.

ByGianni PRATA

RF-SOI Key in MagnaChip IoT Plans

RF-SOI will play a key role in the IoT plans of analog and mixed-signal specialist MagnaChip (read the press release here). The company has launched a task force to address IoT. The statement says, “MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.”

Commenting on the IoT opportunity, YJ Kim, MagnaChip’s interim Chief Executive Officer, said, “We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets. MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”

ByGianni PRATA

Interview: Peregrine’s new Marketing VP on Global 1®, RF-SOI drivers, UltraCMOS 10

Interview with : Duncan Pilgrim, VP of marketing

ASN had a chance to catch up with Duncan Pilgrim, Peregrine Semi’s new VP of Marketing. Here he shares insights into the company’s new reconfigurable RF front end.

Duncan photo

Duncan Pilgrim is the VP of marketing at Peregrine Semiconductor. A 17-year semiconductor industry veteran, he previously served as VP of marketing for Sequoia Communications and held product, strategic and technical marketing roles at RFMD. His strong technical background comes from engineering positions at RFMD, GEC Plessey Semiconductor and Marconi. Pilgrim earned a master’s degree in business administration from Wake Forest University and a bachelor’s degree in electronic engineering from University of Birmingham in the UK. 

 

 

 

 

 

 

Advanced Substrate News (ASN): At Mobile World Congress in February 2014, Peregrine introduced the UltraCMOS® Global 1 reconfigurable RF front-end system. Can you tell us about it?

Duncan Pilgrim (DP): UltraCMOS® Global 1 is an integrated RF front-end solution. The architecture differs from existing solutions because it is 100-percent CMOS-based, which enables all components to be integrated. Global 1 delivers reconfigurability and performance that – for the first time – make possible a single, global SKU that accommodates all 40+ LTE bands and more than 5,000 RF states. The UltraCMOS Global 1 RFFE system includes a 3-path multimode, multiband (MMMB) PA, post-PA switch, antenna switch and antenna tuner; support for envelope tracking; and a common RFFE MIPI interface.

Unique to Global 1 is the power amplifier’s exceptional performance. As anyone who saw our demonstration at Mobile World Congress can attest, the performance figures are truly remarkable. After eight years of research and development, we have introduced the first CMOS SOI power amplifier (PA) to meet the performance of GaAs-based products and exceed the performance of existing CMOS PAs by 10 percentage points. This represents a 33-percent efficiency increase over existing CMOS PAs.

Like all Peregrine products, Global 1 is based on Peregrine’s deep expertise in RF-SOI CMOS. For 25 years Peregrine and its founders have been pioneering RF SOI with the vision of creating an integrated RFFE based on CMOS. Global 1 is the culmination of this vision and is based on Peregrine’s latest advancement in UltraCMOS technology, the UltraCMOS 10 platform.

 

ASN: What markets does Global 1 target?  What are the market drivers?

DP: The market for LTE devices has grown rapidly, and it has put unprecedented demands on the performance of the RF front end (RFFE). Historically, the RFFE has been a collection of products designed independently by a broad range of different vendors on a mix of disparate technologies. This was an acceptable solution before mobile-data demand drove the proliferation of bands and advanced technologies such as LTE and carrier aggregation. Today’s market demands more, but existing RFFE technology has limited OEMs’ ability to deliver a single reference design that works in all global regions – a single, global SKU.

Consider Apple’s recent iPhone 5S launch, which had five SKUs to accommodate different regions. Our research showed that the only obvious difference between the devices was the RFFE content. Had the technology been available for Apple to release an iPhone with a single, global SKU, imagine the cost savings in engineering, validation, manufacturing and supplier and inventory management.

With an exponential increase in RFFE complexity, integration is critical. Only a truly reconfigurable RFFE will enable a single, global SKU, and a reconfigurable RFFE is only possible if the entire system is based on CMOS. Global 1 enables LTE platform providers and OEMs to save time and money by creating a single-SKU design for global markets. With greater flexibility and choice, Global 1 meets the next wave of global, mobile-device innovation.

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ASN: What are the benefits for your customers?

DP: RF design engineers will benefit most from the UltraCMOS Global 1 system because it can dramatically reduce the engineering and validation time required, but Global 1 really benefits the entire wireless ecosystem. Platform providers can develop a single reference platform, reducing reference design development costs and validation time. OEMs can design a single, global SKU, cutting R&D costs, accelerating time to market, streamlining supply chains and improving inventory management. Finally, wireless operators can reduce capital investments in their network with improved RFFE performance, resulting in better coverage and reductions in dropped calls.

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ASN: What are the benefits for the end-user?

DP: Global 1 also benefits the end-user. Consumers can enjoy longer battery life, better reception, faster data rates and wider roaming range.  These impressive benefits are made possible by the properties of CMOS and by RFFE integration.

 

ASN: You mentioned the UltraCMOS 10 technology platform earlier. Can you provide some background on it, and why it’s particularly well-suited to the Global 1 system?

DP: We introduced the UltraCMOS 10 technology platform in October 2013. It is the latest in a long, highly-successful RF-SOI line for Peregrine. The technology leverages Peregrine’s design expertise along with Soitec semiconductor materials and a unique, GLOBALFOUNDRIES fabrication flow to deliver over 50-percent improvement – measured by the Ron Coff figure of merit.  This figure of merit directly impacts key performance metrics such as insertion loss, isolation and product size. UltraCMOS 10 technology delivers both flexibility and unparalleled performance for addressing the ever-increasing challenges of RF front-end design, making it an ideal foundation for Global 1.

 

ASN: Are there other UltraCMOS 10 technology-based products in the pipeline?

DP: Yes, UltraCMOS 10 technology will be the foundation for Peregrine’s mobile wireless products, including our high-performance switches and tuners.  The technology platform gives smartphone manufacturers flexibility and value without compromising quality for devices ranging from 3G through LTE networks. When we introduced UltraCMOS 10 technology in October, we also announced the sampling of the first RF switches built on the UltraCMOS 10 technology platform.

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ASN: When will Global 1 be available?

DP: Global 1 will complete platform integration in 2014 and will be in volume production in late 2015.