Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.
Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.
This year’s program includes:
The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.
Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris
Download the Advance Program
Find all the details about the conference on our website: s3sconference
Click here to go directly to the IEEE S3S Conference registration page.
Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.
S3S Conference
The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928
October 5th thru 8th, 2015
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Join the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.
ST unveils first FD-SOI products – groundbreaking SOCs for set-top-boxes
FD-SOI champion STMicroelectronics has unveiled the company’s first System-on-Chip (SoC) products on FD-SOI. Two multi-core ARM SoC offerings – both for set-top boxes – have been announced. ST credits the 28nm FD-SOI silicon technology with providing highly-efficient RF and analog integration as well as outstanding power efficiency so that set-top box makers can now design very small fan-less systems. The announcements include:
- The Cannes Wi-Fi (STiH390): the first set-top-box SoC on the market integrating 4×4 11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This delivers state-of-the-art Wi-Fi performance and robustness required for reliable video delivery inside the home. (Read the press release here.)
- The new HD HEVC Liege3 family of chipsets for entry Set-Top-Box markets, with flavors for satellite, cable-market and IPTV set-top-box devices. More than just an upgrade of previous-generation devices, the new chipset family combines the latest architectures used in ST’s Cannes products with optimized IPs to deliver future-proof SoCs with high integration. ST says this will enable large-scale migration of entry set-top boxes towards HEVC (High Efficiency Video Coding). All chipsets are pin-to-pin compatible to facilitate design re-use among the different broadcast technologies. Software compatibility with ST’s Cannes SoC family enables OEMs to benefit from the comprehensive ecosystem in order to easily design innovative client boxes on multiple middleware products. (Read the press release here.)
Both are currently sampling to lead customers.
TowerJazz and TowerJazz Panasonic Semi Co sampling best-in-class sub-90fs Ron-Coff RF-SOI on 300mm wafers for Next-Gen 4G LTE and IoT Apps
Global specialty foundry TowerJazz and TowerJazz Panasonic Semiconductor Co. (TPSCo), the leading analog foundry in Japan, have announced breakthrough RF-SOI technology for next-generation 4G LTE smartphones and IoT devices. Through a collaborative effort, TowerJazz and its majority owned subsidiary, TPSCo, have developed a new 300mm RF-SOI process that can reduce losses in an RF switch by as much as 30% relative to current technology, improving battery life and boosting data rates. The technology achieves a record Ron-Coff figure of merit of sub-90fs and is now being sampled to a lead customer. (Read the press release here.)
X-Fab Interview: SOI Solutions for analog/mixed-signal, high-voltage, high-temperature and MEMS Applications
With five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.
Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?
Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.
Tilman Metzger, Product Marketing Manager for the X-Fab Group. (Courtesy: X-FAB)
Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.
ASN: When did X-Fab first start offering SOI and why?
TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.
ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?
TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.
Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.
ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?
X-FAB headquarters in Erfurt, Germany (Courtesy: X-FAB)
TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.
Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.
ASN: When and why do your customers choose an SOI-based process?
TM: Typically, we see two types of SOI customers:
- Those that tried and failed a particular design in a BCD/Bulk technology and hence turned to a SOI solution; and
- Those that focus on SOI technology right from the start due to IC or system requirements (or past experience). Some of the challenges of such designs may include:
- Very high temperature of 175-225°C
- Resistance to EMI* or stringent EMC and ESD requirements
- Latch-up concerns
- Negative voltage swings / inductive loads
- Stringent noise immunity / cross-talk requirements
- Low leakage at high temperature
- Aggressive time-to-market requirements
ASN: Can you expand on the time-to-market (TTM) issue a bit?
TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.
ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?
TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.
ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?
TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..
ASN: Can you tell us more about X-Fab’s SOI offerings?
X-FAB cleanroom in Kuching, Malaysia, where the company runs their new XT018 SOI process. (Courtesy: X-FAB)
TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)
Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.
XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.
XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.
ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?
X-FAB MEMS Foundry received the “MEMS Foundry of the Year” award at the Best in MEMS & Sensors Innovation Awards ceremony, as part of the MEMS Industry Group’s 10th annual MEMS Executive Congress® held in Scottsdale, Arizona in November 2014. (Courtesy: X-FAB)
TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.
For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.
We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.
ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?
Chips manufactured by X-FAB go into key automotive systems. (Courtesy: X-FAB)
TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.
We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.
We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.
ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?
TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.
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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.
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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge
**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.
Don’t Miss Leti Days and FD-SOI Workshop (Grenoble, 22-26 June)
CEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).
On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.
The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.
The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.
If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.
FinFET or FD-SOI? Designers have a real choice, say experts
Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.
Is there a place for FinFETs? Of course there is. If it’s a really big digital chip – no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.
But is that really where most designs are?
(Photo credit: Monterey County Convention and Visitors Bureau)
If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.
Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.
EDA experts weigh in at EDPS
Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.
The session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.
And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”
EDPS 2015 panelists debate FinFET vs. FD-SOI. (Left to right: Marco Brambilla (Synapse Design); Kelvin Low (Samsung); Boris Murmann (Stanford); Jamie Schaeffer (GlobalFoundries). (Image courtesy: Richard Goering and Cadence)
In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:
- Kelvin Low, Sr. Director Foundry Marketing for Samsung
- Boris Murmann, Stanford professor and analog/mixed-signal expert
- Marco Brambilla, Director of Engineering at Synapse Design
- Jamie Schaeffer, Product Line Manager at GlobalFoundries
The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
There you have it!
Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).
Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.
So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.
SOI Radiation Detector Workshop – Registration Extended (SOIPIX2015 – June, Japan)
International research teams working on or interested in the far-reaching SOIPIX radiation-detector project have a workshop coming up in June. The project was originally started by KEK* scientists to develop a new detector technology and quantum beam imaging for high-energy particle physics. As research teams around the world (including Japan, USA, China and Europe) joined to take advantage of the multi-wafer project runs, it soon expanded to include more applications. (To learn more about the program, click here.)
Leveraging the SOIPIX strategy of SOI-based monolithic sensor-electronics integration, applications are now being developed in areas such as medical (x-ray sensors and radiotherapeutic systems), materials research, nuclear physics, astrophysics, electron microscopy and industrial uses (such as x-ray inspection systems).
(Here at ASN, we covered the project and its implications for medical imaging back in 2010 – click here to read that piece.)
The next workshop, SOIPIX2015, will take place at Tohoku University (Sendai, Japan) 3-5 June 2015. Registration has been extended until 22 May 2015. Click here for registration information.
*KEK is Japan’s High Energy Accelerator Research Organization.
Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016
Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.
ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.
Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?
Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.
ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?
SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.
ASN: At what point in the design process do you typically come in? What sorts of services do you offer?
SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.
ASN: What do you see as the advantages of FD-SOI?
SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.
An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.
We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.
ASN: Designers of what kinds of chips should be thinking about FD-SOI?
SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.
ASN: Why do they ultimately choose it? Why do they hesitate?
SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.
ASN: Are there special considerations designers should think about before starting a project in FD-SOI?
SB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.
ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?
SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.
Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.
ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?
SB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market
ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?
SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.
ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?
SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.
We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.
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Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.
New Semico Study on SOI Apps, Opps & Markets
Research and consulting group Semico has issued a new report entitled SOI Update 2015: Finding New Applications (for information on getting a copy of the report, click here). As described on the Semico website: “With the recent growth in RF-SOI for switches and integrated solutions for RF functions such as power amplifiers and transceivers, the opportunities for growth in SOI wafer demand have once again garnered a lot of attention. In addition, as the industry transitions to very complex and expensive finFET technology, SOI is providing a high performance, low power option to semiconductor vendors who do not want take on the challenges of finFETs. This report explores the markets, products and outlook for SOI wafer adoption over the next five years.”
28nm FD-SOI cryptocurrency ASIC first to debut in silicon, surpasses expectations with 0.45V operation
SFARDS’ SF3301 cryptocurrency ASIC is the world’s first chip to use 28nm FD-SOI. Surpassing expecttions, it operates at a stunning 0.45V. (Courtesy: SFARDS)
Right on schedule, the SFARDS cryptocurrency ASIC on 28nm FD-SOI has made its debut in silicon, and is surpassing expectations. In what is clearly a stunning success, the company announced that the ASIC’s lowest working voltage is 0.45V. This means it operates stably at a power supply voltage that’s about half that of competing 28nm offerings.
An article published on the SFARDS website (see the whole thing here) said, “Using the latest in FD-SOI processing technology, SFARDS has successfully completed its 28nm SF3301 dual-algorithm ASIC chip. The SF3301 is the world’s first chip to use this manufacturing process and is at the same time the world’s first 28nm dual-algorithm (SHA-256 & Scrypt) chip, capable of mining these two algorithms simultaneously or singularly.
“SFARDS’ SF3301 fully utilizes the advantages of the FD-SOI technology. This brings increased forward body bias; the chip is operational at lower voltage while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V.”
As noted in ASN’s Buzz in March 2015 (read it here), cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips. As well-explained in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.