EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.
Here’s a recap of what the Cadence folks said. (I’ll cover the Synopsys and Silvaco presentations in my next posts.)
At the Shanghai FD-SOI Forum. Dr. Qui Wang, VP & Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.
In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.
To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.
Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World — Cadence EDA & IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.
He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.
His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow).
Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)
Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.
For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry’s PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.
And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).
Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.
GlobalFoundries and the Chengdu municipality plan to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. They’ve announced an investment of more than $100 million, which is expected to attract leading semiconductor companies to Chengdu, making it a center of excellence for designing next-generation chips in mobile, IoT, automotive and other high-growth markets.
This follows hard on the heels of the partners’ announcement that they’re building a 300mm fab in Chengdu to meet accelerating global demand for GF’s 22FDX® FD-SOI technology.
The partners’ plan is to establish multiple centers focused on IP development, IC design and incubating fabless companies in Chengdu, with the expectation of hiring more than 500 engineers to support semiconductor and systems companies in developing products using 22FDX for mobile, connectivity, 5G, IoT, and automotive. There will also be a focus on creating partnerships with universities across China to develop relevant FD-SOI coursework, research programs and design contests.
Support for the plan is pouring out from across the ecosystem (read the press release here for all the quotes).
“This new design and IP ecosystem in Chengdu is exactly what the Chinese fabless industry needs to take advantage of the game-changing features of FD-SOI, ” says Dan Hutcheson, CEO and Chairman of VLSI Research. “The initiative is well positioned for success, considering GF’s track record of positive private-public partnerships to grow ecosystems around its fabs in Germany and New York.”
SOI Consortium member GlobalFoundries is teaming up with the Chengdu municipality to build a fab in western China offering FD-SOI (see press release here). The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX®, GF’s 22nm FD-SOI process technology. The Chengdu fab is expected to begin volume production of 22FDX in 2019.
In Germany, GF plans to grow the overall FD-SOI capacity of its Fab 1 facility in Dresden by 40 percent by 2020. GF says they need the new capacity to meet demand for IoT, smartphone processors, automotive electronics, and other battery-powered wirelessly connected applications. Dresden will continue to be the center for FDX technology development. GF engineers in Dresden are already developing the company’s next-generation 12FDXTM technology, with customer product tape-outs expected to begin in the middle of 2018.
In Singapore, GF will also add new capabilities to its industry-leading RF-SOI technology.
The panel discussion rounding out the day at the recent FD-SOI Forum in Shanghai ended an exciting week (GF’s 12nm FD-SOI & ecosys, Sony’s FD-SOI GPS in the Huami watch) on a decidedly optimistic note. Here’s a quick rundown of some of what was said.
(As soon as the presentations given earlier in the day are posted, we’ll take a quick cruise through those, too.)
Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits started it off with the reminder that for anything “always on” in IoT, FD-SOI’s always better. They had a terrific experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here). The port from 28 bulk took 2 1/2 months (vs. to FinFET, which took almost 6). Even without using body bias, they got performance up by around 15% and leakage down by about 30% (he added that with body bias, they could get five times that).
He compared porting to FD-SOI to playing high school ball, vs. a port to FinFET which is like competing in the Olympics. ESD was different, but not a big deal – you just need to “read the manual”. Heating? Nothing an engineer can’t resolve. For IoT, FinFETs are like using a cannon to shoot a mosquito, he quipped.
He later ticked off a few more advantages of FD-SOI for the IoT design community: system cost, lower power – and here’s a particularly interesting observation – cheaper packaging. They were able to do wire bonding, so they were able to package a wearable video app in a plastic capsule. All things considered, FD-SOI offers the perfect solution, he said (and now he’s got silicon with “dramatic results” to prove it), adding that the IP guys need to evangelize this.
GloFo VP Subramani Kengeri took a moment to look back before he looked forward. “FD-SOI is not new,” he reminded us. It was explored and researched for a decade. But at the beginning, CPUs were driving the industry, and everyone else followed suite. But now in mobile and IoT, RF is becoming more important, and what was good for the CPU is no longer what’s good for everything else. He tipped his hat to Soitec, ST and Leti, who “kept the lights on” and kept driving FD-SOI forward. Now with 5G on the horizon, FD-SOI is the enabler, he added.
He also noted that FD-SOI gets you the maximum memory onchip, and that with 12FDX, we’ll be seeing the world’s smallest SRAM. So that opens a new degree of freedom. The EDA partners have been working on automating body bias in the PDK for greater power management. He cites an ARM core with on-demand performance that can be used “intelligently”. Is it complicated? Not really, he says, especially if it’s automated. In fact he sees body bias opening the market for “extraordinary, innovative products” very soon. Key IP is in place. And it’s not just for IoT: aside from high-end CPUs, FD-SOI is optimal for everything. “Everything’s happening now, and it’s moving really fast,” he said.
SOI wafer leader Soitec VP Christophe Maleville was asked if he saw any limit on manufacturing the ultra-thin wafers for the 7nm node. No problem, he said – they can do those wafers with 4nm of strained top silicon and a 10nm layer of insulating BOX. They’ve been working on FD-SOI wafers for over a decade, he reminded us, with Leti, IBM and ST. Back in 2013 when ST announced the Nova-Thor hitting 3GHz (or 1GHz at just 0.6V), everything was in place: the metrology was ready, reliability was controlled.
Today they’ve got a 15nm BOX layer in manufacturing, with no limits in moving to 10nm for customers going for very low power. For the strained top silicon needed for the 7nm node, they spent years working on strain with IBM et al in Albany, so they’re not starting from scratch. That substrate will be mature in just two years, so from a substrate point of view, he said, “7nm is no problem”.
In response to a follow-up question from a well-known analyst in the China tech industry, panel moderator and Verisilicon CEO Wayne Dai said that the design community in China has the skills to do FD-SOI, no problem. He’d like to see more IP, but FD-SOI has powerful advantages in terms of cost, analog/memory and back biasing.
Dai then asked the panelists if they thought we’d be seeing a foundry in China opting for FD-SOI by next year – all but one said yes. One thing all the panelists agreed on, however: they all expect to see FD-SOI products (and lots of them) on the stage at the Shanghai FD-SOI forum in 2017.
Sony’s 28nm FD-SOI GPS rolling out in the Xiaomi Amazfit smartwatch is “…a big win for Sony” and “…an even bigger win for FD-SOI’s promoters,” said Junko Yoshida of EETimes (see Sony-Inside Huami Watch: Is It Time for FD-SOI?). Then she adds:“Huami’s watch decidedly demonstrates the technology’s claim to ultra-low power consumption.”
Xiaomi is a subsidiary of Huami, which lays claim to being the second largest manufacturer of wearables in the world. So it really is a big win. What’s more, the Amazfit, says Xiaomi, is “…the world’s first smartwatch with a 28 nm GPS sensor”.
Sony has been releasing evolving details of the chip at various conferences over the last few years (including SOI Consortium forums). To get their ISSCC paper, 26.5 A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI (February 2016) from IEEE Xplore – click here.
(Image courtesy xiaomi-mi.com)
12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).
The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”
Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”
The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”
GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.
The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.
“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”
Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).
Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.
Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.
Initial FDXcelerator Partners have committed a set of key offerings to the program, including:
Additional FDXcelerator members will be announced in the following months.
FD-SOI makes sense for China. That was the key message SOI wafer leader Soitec made in a press conference on FD-SOI for a select group of journalists just before Semicon China this spring. News then quickly spread, and resulted in over 150 FD-SOI articles in the top China technology and business press.
Soitec also put together a super FD-SOI resource page, with lots of information in Chinese (you can see it here).
Soitec execs Thomas Piliszczuk, SVP of Marketing & Biz Dev and Christophe Maleville, SVP of the Digital Electronics BU joined forces with the CEO of the Chinese wafer company Simgui and the VP of the National Silicon Industry Group (NSIG). They made the case that FinFETs, bulk and FD-SOI will co-exist, FD-SOI is an excellent technology for China on two fronts:
It was a powerful set of messages and clearly resonated throughout the press. Here’s a quick look (with a little help from Google Translate…) at what some of the top publications had to say.
The ChinaByte article was one of many that reported on the key points that the Soitec folks made at their press conference, leading with the headline that FD-SOI can help the China innovation blueprint. Other points included:
With a daily page views of over 1.7 million, CCINET is an influential site. The headline they ran was about how Soitec has promoted the ecosystem of FD-SOI and shares its innovate engineered substrates in China (link here). The thrust was that FD-SOI represents an opportunity for China. It covered the basics of FD-SOI, Soitec’s role as the leading global engineered substrate expert and partnerships in China with Simgui and Sitri, and FD-SOI’s strong ecosystem.
In a long and detailed piece, EETimes-China documented Soitec’s decade-long history in China, explained the special role of Soitec’s Smart CutTM technology in manufacturing the ultra-thin wafers for FD-SOI, then covered the scope of the ecosystem and the value propositions. There was also a follow-up piece by International Editor Junko Yoshida in the global edition of EETimes (see here).
Many publications focused on how Soitec and FD-SOI supports China’s innovation plan. They include: Power System Design; ECCN; Electronic Products China; 21ic; Electronic Engineering & Product World; EC.HC360; Microwave Journal; and China Electronic Market
China Electronic News noted how FD-SOI supports “Made in China 2025”. The headline of the China Business Journal article (which got a lot of WeChat attention) positioned FD-SOI as a new choice for the semiconductor industry, and a chance for China become an industry leader. EEWorld cited Simgui’s and NSIG’s affirmation that FD-SOI adoption is moving fast and will have a bright future in China. EEFocus looked at how FD-SOI compares with FinFETs (very well!), and cites Soitec’s Maleville as saying FD-SOI represents a 6 million wafer/year opportunity in China by 2020.
SST/China called FD-SOI the best choice for mobile and IoT. Of course we can’t cover all the other articles here, but with the Soitec press conference having generated over 150 pieces in the China tech and biz press, that message is now clearly out there.