Here’s why the embedded community should care whether the chips they use are built on FD-SOI. FD-SOI has “…dramatically improved the landscape for power efficiency,” NXP VP Joe Yu explains in a recent Embedded Systems Engineering piece (you can read it here). He gets into the hows and whys of the i.MX7ULP chip design, taking a deep dive into the things that the embedded folks really care about.
He details how FD-SOI decreases leakage and dynamic power, including the roles played by forward and reverse body biasing. He then goes on to explain why it’s better for analog, and how it prevents latch-up.
FD-SOI enables new features, too, he points out, like ultra-low power consumption and deep sleep suspend. And perhaps most importantly, he explains how bursty high-performance and ultra energy efficiency are dynamically traded off on an as-needed basis. “Engineers no longer face a forced selection: low-power processor or high-performance processor,” he say. “Rather, the selection for performance or power efficiency can be made instantaneously, as needed, without having to reconfigure.”
All of this plus the rich graphics and user interface FD-SOI enables makes the i.MX 7ULP perfect for “…IoT edge devices, as well as smart home controls, building automation, portable patient monitoring, wearables, and portable scanners.”
This is an excellent read: highly recommended.
Of course, ASN covered the i.mX7ULP when it was first announced (on Samsung’s 28nm FD-SOI) last year – you can still read our coverage here. But it’s good to see the company explaining to their customers how FD-SOI will change the way they build products. BTW, you can get all the i.MX7ULP product details on the NXP website here. NXP has also put together a nifty video on the i.MX7ULP – see it here.
The foundries sent their top guns to the FD-SOI Forums organized by the SOI Consortium and its members in Shanghai and Nanjing. This is a quick recap of what they said.
“With FD-SOI, we can deliver a level of integration never before possible,” said GlobalFoundries CEO Sanjay Jah in his Shanghai talk, Winning With SOI. The ecosystem they’re building is covering both design and supply. He showed a video of the new fab, which is going up at an enormous speed in Chengdu, China. It’s huge: a half-kilometer long on one side. And it will start producing wafers in H218, ramping up to a million/year.
FD-SOI is past the discovery phase now, he continued. They’ve got 135 engagements and 102 PDKs downloaded. In China alone, they have ten customers taping out 15 products. The key is going after high-growth markets, including mobility, IoT, RF/mmW and automotive (see picture above). “We see intelligence migrating to the edge,” he said.
With 22FDX®, there are 11 fewer mask steps than industry standard 28nm HKMG processes, he said. Back bias is a big differentiator, reaping benefits without penalties and shortening time-to-market. eMRAM is also a big driver of interest. The IP – both foundation and complex – is silicon-proven: you can measure it. The FDXceleratorTM program now has 35 partners.
He also touched on RF-SOI, where GF is #1 in terms of market share.
“I’m very excited about the future for us,” he concluded.
In the Nanjing SOI forum, GF’s head of China sales, Zhi Yong Han gave an excellent presentation that is posted on the SOI Consortium website (you can get it here). He emphasized that they are educating designers to help them take advantage of the FD-SOI for advanced devices, as well and working with universities. The result is that they’re seeing significant growth in the Chinese market.
Zhi Yong Han also highlighted the excellent performance of GF’s RF-SOI offering, and the huge capacity they’re building out. NB-IoT clients are now approaching them, he added.
“E.S. stands for Engineering Sample,” quipped Dr. E.S. Jung, EVP/GM of the foundry business for Samsung Electronics. A very energetic speaker, his talk covered Cutting Edge Technology from a Trusted Foundry. (Samsung Foundry is now a standalone business unit.)
Samsung has seven major 28nm FD-SOI customers, and has taped out over 40 products. This coming year a number of products will be taking off in mass production, he said.
eMRAM (which only required three additional mask steps) is the newest addition to the family of embedded non-volatile memories and it offers unprecedented speed, power and endurance advantages (see the press release here).
Regarding back bias in the IP, he said they’ve solved it working with their suppliers, EDA vendors and customers. Migrations will re-use that IP.
At the Nanjing SOI forum, VP of Samsung Foundry Suk Won Kim looked at design methodology in his talk, 28FDS Samsung Foundry Platform. It’s easy to implement your SoC with FD-SOI technology, he said, explaining how PPA and cost/transistor makes 28FDS an optimal node. The PDK – including RF – are ready for high volume production. There is no design overhead: the differences between FD-SOI and bulk are not difficulties, he emphasized.
For 28FDS, the full spectrum of the ecosystem is available: design enablement, advanced design methodologies, and silicon-proven IP. Samsung has a body bias generator, and the design methodology takes care of checking the body bias integrity. In terms of the physical design, there is awareness in the floorplan for body biasing and flip-well devices. In terms of timing sign-off, there’s almost no change – in fact there are fewer PVT corners. The flow for power integrity sign-off doesn’t change. The RTL-to-GDS flow is about the same – and where they diverge, designers are embracing the differences.
And for those looking ahead, the PDK for 18FDS evaluation will be available soon.
BTW, there were five days of events in Shanghai and Nanjing, with over 50 presentations given in ballrooms full-to-bursting. As noted in my previous post, China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth, many (but not all) of the presentations are now available in the Events section here on the SOI Consortium website.
So in future posts, we’ll cover the EDA/IP companies, design tutorials and user presentations for both the FD-SOI and RF-SOI China events — including those not posted. Stay tuned!
As noted on the Lattice website, their business is to provide “… smart connectivity solutions powered by our low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide.” And at their last Analyst and Investor Day, Lattice CEO Darin Billerbeck did a brilliant job explaining their strategy of targeting the “new edge”, where IoT devices really live.
At EW, David Manners talked to Lattice COO Glen Hawk, who told him they’re moving all their new products to 28 nm FD-SOI over the next couple of years. Manners says they benefit from the “…flexibility, low-power and low-cost of FD-SOI”. (Read the full article here.)
A Lattice spokesperson told Peter Clarke at EENewsAnalog that, “Lattice will be migrating to 28 nm FDSOI for new products, which we believe will enable us to achieve 10x lower power with the highest performance devices for edge connectivity and edge computing applications. Existing products will remain on their existing nodes and foundries.” (Read the full article here.
And over at EE Journal, Kevin Morris spent a day at Lattice. Rather than copy the traditional FPGA companies that are going for the high end with advanced FinFET processes, he explains, “Lattice uses FD-SOI processes to milk out the most performance possible with the tiniest power budgets and lowest device cost.” The result he predicts is that, “Lattice will own the edge where pennies and millimeters and microwatts are at a premium.” (Read the full article here.)
When the next generation of NXP’s ground-breaking “crossover processors” come out in 2018, they “…will use a fabric of i.MX 7 and 8 processors manufactured by using a 28-nm FDSOI process,” and they “…will be more spectacular and complex.” That’s what NXP’s senior vice president and general manager of microcontrollers Geoff Lees recently told EETimes International Correspondent, Junko Yoshida (see the full article here).
NXP announced the i.MX RT series during ARM Techcon (see press release here). Essentially they represent a convergence between application processors and MCUs. With the high performance and functional capabilities of applications processors, but with the ease-of-use and real-time deterministic operation of traditional MCUs, NXP sees applications in audio subsystems, consumer and healthcare, home and building automation, industrial computing, motor control and power conversion.
They’re calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It’s NXP’s new i.MX 7ULP general-purpose processor, and it’s on 28nm FD-SOI. They’ve got a nifty video summing it all up – you can watch it here.
With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.
The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.
The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.
With the i.MX 7ULP, NXP’s targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it’s designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)
The i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It’s got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors.
NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.
NXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.
In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages:
Large dynamic gate and body biasing voltage range
Domain and subsystem optimization with custom standard cell library with mixed voltages
Low quiescent current (Iq) bias generators
Enhanced ADC performance with unique FD-SOI attributes
Fail Safe I/O for simplified low power system design
To that, add a note about security. As the chip’s fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it’s needed.
Two other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP’s results.
“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”
NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.
“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”
So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.
— By Adele Hars, ASN Editor-in-Chief
As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.
If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)
To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:
Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.
Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.
Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.
Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.
Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.
RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.
Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.
Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.
Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.
But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”
Next up: i.MX 8 for automotive +
At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.
We’ll cover it in an upcoming ASN blog, so stay tuned!
— By Adele Hars, ASN Editor-in-Chief
Samsung is adding two embedded NVM (non-volatile memory) options to its 28nm FD-SOI line-up, Kelvin Low told EETimes‘ Peter Clark in a recent interview (read the whole piece here).
Low, who heads up marketing and bizdev for Samsung Foundry, indicated the following roll-out for 28nm FD-SOI:
28nm FD-SOI is on the Freescale roadmap for two key platforms in the company’s flagship i.MX line of embedded application processors:
This was shown in a presentation by Freescale VP Ron Martino during the Shanghai FD-SOI Forum. Entitled Smart Technology Choices and Leadership i.MX Applications Processors (you can download it here), it shows how increasing integration of diverse components and longer lived nodes are driving this move. That’s coupled with the “explosive” growth in smart vehicles and smart devices in the face of rising die costs.
Using SiTimes’ SOI-MEMS based oscillator can extend battery life by a full day in some apps, Piyush Sevalia, Executive Vice President, Marketing for SiTime explained in a recent Planet Analog piece (read the whole thing here).
The traditional timing device is a quartz (passive crystal) resonator, which doesn’t draw any power itself. But it doesn’t save any either. As Piyush describes:
In a portable audio application for example, a SiT8021 oscillator operating at 3.072 MHz draws only 60 μ A compared to a quartz oscillator at 2.5 mA. In this case, the power consumption is 98% lower. This can effectively extend battery life by a full day – a huge improvement.
SiTime is a Bosch spin-off that’s now part of Megachips Corporation. The SiTime CTO first described their SOI-MEMS fabrication technology for ASN back in 2009 (read that here). Since then, they’ve shipped more than 300 million devices and captured 80% market share. Click here for more about SiTime’s SOI-MEMS solutions in ASN.
RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.
In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.
The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.
IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.
Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.
He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.
In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.
Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.
ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)
In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.
With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.
Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.
Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.
More Workshops Coming
If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.