RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.
In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.
The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.
IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.
Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.
He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.
In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.
Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.
ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)
In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.
With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.
Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.
Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.
More Workshops Coming
If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.
More good news: Cisco is working on a 28nm FD-SOI chip. This additional boost to FD-SOI momentum was revealed during the Panel Discussion at the recent FD-SOI/RF-SOI Workshop in San Francisco. The EETimes coverage (which also revealed that Freescale’s putting its next-gen iMX7 microprocessor on 28nm FD-SOI – you can read it here) was quickly shared hundreds of times on LinkedIn.
SemiWiki’s Dan Nenni moderated the panel, which addressed Advantages and Opportunities when Designing with FD-SOI. Panelists included Marco Brambilla, Director of Engineering, Synapse Design; Wayne Dai, Chairman, President & CEO, VeriSilicon; Kelvin Low, Sr. Director, Foundry Marketing, Samsung SSI; Philippe Magarshack, CTO, STMicroelectronics; and Guntram Wolski, Principal Engineer at Cisco Systems.
In case you missed it, we covered the morning’s FD-SOI presentations in a previous post – click here to see it. As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience. In the next ASN post we’ll cover the RF-SOI presentations.
There was lots of anticipation going into the panel discussion, and it turned out to be one of the best parts of what was already a very successful day. There were lots of questions raised, and people commented afterwards that they appreciated that answers were candid and straightforward, while clearly being extremely supportive of FD-SOI.
Kelvin was asked about the positioning of FD-SOI vs. FinFET at Samsung. He explained that there is no conflict, as each addresses a different set of needs. But 28FD: that’s a sweet spot, he reiterated.
He added that we need more FD-SOI seminars and workshops for the design community, to make people feel comfortable. (And those are in the works!)
It was during this panel discussion that Guntram confirmed that Cisco is working on an FD-SOI based chip. Asked about what he sees as the value of FD-SOI technology, he responded:
Asked why Cisco seems to be alone in adopting FD-SOI, he parried: because CIsco is a leader not a follower! He also confirmed that they’re working with all the foundry partners.
Wayne said he sees IOT/wearables as big opportunity for FD-SOI, since they’re power sensitive apps. He commends ST for opening its IP and breaking the chicken-egg issue. He added that with multi-project wafer (MPW) runs from both Samsung and ST, there will be a lot of work on FD-SOI that will further demonstrate the value. Designing in FD-SOI is no different than bulk, he reminded the audience, adding that he’s expecting FD-SOI will be a three-node solution.
When someone asked if FD-SOI is so good, why is nobody manufacturing FD-SOI chips, Kelvin pointed out that there are three foundries in place. They have a solution for double patterning, the ecosystem is now in place, and Samsung will have a fully qualified foundry ready for risk production in March, so stay tuned !
Wayne added that 14FD can be better in many cases than FinFET, and Philippe reminded the audience that Sony is designing with FD-SOI. We’ve passed the critical point.
Asked about the value of FD-SOI in analog design, Philippe noted that quick switching of Vt with FD-SOI is 10x more efficient than bulk . When asked about 14nm cost, he responded that there are savings in limiting or removing double patterning in the backend and the middle of the line. Even with some remaining double patterning, there are 3-4 fewer than FinFET, and 10 fewer mask levels than FinFET.
When someone asked about timing and if it’s too late for 28FD with the leading edge already designing in 14nm FinFET, Kelvin responded that FinFET is sexy, but you need to look at the practical side and value of low power. Guntram said he saw many high volume and low power opportunities at 28nm.
Dan Nenni concluded with the reminder that on SemiWiki, for the last four years the #1 search term has been and continues to be “low power”.
The clear take-away message from the panel was that the FD-SOI solution is real!
In the next ASN post, we’ll review the SF workshop presentations on RF-SOI. (If you’re not already signed up for ASN’s email notifications of new posts, you can do it here.)
The FD-SOI/RF-SOI Workshop in San Francisco last week was a huge success. Over 150 people from over 80 companies attended the all-day event. There were excellent presentations, animated Q&A sessions, and lots of networking going on over coffee, lunch and cocktails. It generated excellent press (click here to see the EETimes feature) and lots of activity on LinkedIn and Twitter.
Everyone agreed it was an outstanding day, with all the presenters emphasizing the value, availability and ramp of FD-SOI. Feedback from the presenters indicates that the workshop spurred a significant boost in interest and opportunities. As one participant noted, “This was very credible.”
If you didn’t make it to SF, we’ll cover the highlights in three ASN posts over the next few days (yes, it was that good!). Here in Part 1, we’ll cover the FD-SOI presentations. In Part 2, we’ll listen in on what was said during the panel discussion on FD-SOI. And in Part 3, we’ll take a look at the RF-SOI presentations. The actual presentations will all be posted shortly on the SOI Consortium website – keep checking back. But for now, here are some snapshots.
ST’s CTO Philippe Magarshack presented on FD-SOI Advantages for Applications and Ecosystem. He was very clear on the value proposition of FD-SOI, with multiple examples (and a tip of the hat to Soitec, which enabled ST with industrial FD-SOI substrate).
ST’s now got 18 active FD-SOI projects underway, he said. What’s driving it? FD-SOI is all about integration, he pointed out: digital, analog/mixed-signal and RF for starters. Beyond mobile, he cited three key application segments:
He also provided a summary of the key design advantages:
With foundry partner Samsung and a complete design platform, the ecosystem is now in place, he concluded.
Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI had a very clear message on the FD-SOI foundry offer: they are in business!
In his presentation, 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm, he covered the technology migration history: scaling, material then structure innovation.
Driving home the message that 28nm will be a long-lived node, he said the PDK’s ready, foundry services are ready and they’re taking orders. (In fact, there was a whole team from Samsung there, answering additional questions and following up with prospective customers during the breaks.)
Kelvin showed manufacturability and reliability data, and PPA (power, performance, area) benchmarks (see slide).
For wearable apps, of course, low power is a must. Here, body biasing and low Vdd (supply voltage) are key, and again, 28nm FD-SOI shines (see slide).
Next came excellent presentations by the EDA giants.
Mike McAweeney, Sr. Director IP Product Sales presented Synopsys FD-SOI IP Solutions.
Amir Bar-Niv, Senior Group Director, Product Management, Design IP at Cadence presented FD-SOI: Ecosystem and IP Design.
These were largely the same presentations given by these companies at the Tokyo FD-SOI workshop in December. Click here for ASN coverage of that event and details on those presentations.
Ben-Hamida, High Speed Analog Design Manager, Ciena presented the company’s view of the value of FD-SOI in their new 100Gb/s transceiver (see slide). He was very enthusiastic in his support of FD-SOI, and its ability to deliver on its promises.
And finally, Shirley Jin, Sr. Director of Engineering at design house Verisilicon presented very compelling benchmarking data on an ARM Cortex A-7 in her presentation, 28nm FD-SOI Design/IP Infrastructure (see slide). Shirley gave a similar presentation in Tokyo in December. Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. Her presentation presented extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.
Members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.
And stay tuned for Part 2 of ASN’s SF Workshop coverage – where we’ll cover the panel discussion, and the big news that Cisco’s on board with an FD-SOI chip of their own. Part 3 will cover the RF-SOI presentations, and the massive rate of innovation seen there.
NXP recently expanded its GreenChip line of SOI-based power supply controller ICs with the new TEA1832TS (click here for more product info). Here at ASN, we first covered this line back in 2011 (see that Buzz here), and NXP’s been adding to it ever since.
Smart, green power supplies are one of the most important ways that designers reduce the power consumption of modern electronics. The reason NXP has been using SOI for over 15 years is well explained in this ASN piece from 2009 – read it here.
The TEA1832TS is a low-cost Switched Mode Power Supply (SMPS) controller IC intended for flyback topologies. It makes the design of low-cost, highly efficient and reliable supplies easier by requiring a minimum number of external components. The device is especially suited for medium power applications.
Soitec has developed an innovative metrology and metric for ensuring that devices built on our latest SOI wafers for RF will meet the draconian demands of LTE-Advanced (LTE-A) and 5G network standards.
For smartphones and tablets to handle LTE-A and 5G, they need RF devices with much higher linearity than those running over the current 2G, 3G, 4G and LTE network generations. These next generation network standards require mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)
Soitec recently announced eSI90, our newest generation of trap-rich, high-resistivity SOI wafers for LTE-A and 5G. eSI90 extends our existing line of eSITM (enhanced Signal Integrity) wafers, the first generation of which are currently being used by leading manufactures to produce more than a billion RF devices every quarter.
This article gives an overview of how Soitec developed a new metric using innovative metrology on its wafers in order to predict the RF performance of final devices manufactured on eSI substrates. (Readers wanting greater detail can also consult our complete white paper on the subject, which is freely available to download here.)
To address the different communication standards and functions used in front-end modules, Soitec, the leader in SOI technology, has developed two flavors of RF-SOI products – high-resistivity (HR)-SOI and Enhanced Signal Integrity TM (eSI) SOI – both of which are compatible with standard CMOS processes. While standard HR-SOI wafers (which we introduced over a decade ago) are capable of meeting 2G or 3G requirements, eSI SOI can achieve much higher linearity and isolation specifications, allowing designers to address some of the most stringent LTE requirements. (We detailed how advanced RF design challenges are solved by eSI wafers in a 2013 ASN article – you can still read it here.) This paves the way for integrating more functions on a device with better RF performance at competitive cost.
eSI wafers leverage the addition of a “trap-rich” layer to high-resistivity (HR) SOI wafers, an approach that was developed by UCL and Soitec (that project was covered in an ASN piece explaining the technical details at the time – you can read it here).
The IIP3 linearity requirements for 3G are +65dBm. For LTE, they increased to +72dBm, and for LTE-A, they are over +90dBm. For RF designers, this has added substantially to the complexity of RF Front-End Modules (FEMs), and entails multiple changes for each of the main functions: switches, power amplifiers, power management and antenna tuners.
These latest front-end modules need to support more bands, higher frequency bands from 700 MHz to 3.5 GHz, larger bands from 20 MHz to100 MHz and carrier aggregation downlink and uplink, sometimes on adjacent bands. This means:
To meet the required performance, many changes are happening at all levels, from systems, architectures, design, manufacturing processes, devices – right down to where it all starts: the substrates. The substrates on which RF devices are manufactured have a significant impact on the level of performance that the final chips will be capable of achieving.
To quantify the performance designers can expect from an eSI SOI substrate, Soitec has now developed an innovative characterization method based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide. This solution is used today throughout the Soitec eSI product line to ensure the substrates will enable the expected RF performance in the finished devices.
We predict the RF harmonic distortion performance of the substrate immediately after the eSI SOI substrates are fabricated and before any devices are manufactured on them. This prediction is provided through a metric we call the harmonic quality factor (HQF).
HQF correlates with the second harmonic distortion generated from a 900-MHz signal applied to a coplanar waveguide (CPW) deposited on the substrate.
The CPWs are implemented on sample test wafers by depositing aluminum metal lines on the buried oxide of eSI SOI wafers after the Smart Cut process has been completed and the top silicium removed.
Then a 900-MHZ fundamental tone is applied on one end of the CPW line and the HD2 signal is measured at the other, providing a value of the HD2 generated by the substrate. Then, using the same wafers, a Spreading Resistance Profiling (SRP) technique measures the resistivity of the material at different depths under the buried oxide.
Next, we use a proprietary algorithm to compute the series of measures. The algorithm, tuned to match various HD2 values, takes into account the resistivity of the substrates weighted by the depth of the measure, and gives us the HQF.
Soitec has implemented this metrology on its production eSI SOI wafers and is sampling products to carry the HQF measurement.
To address different market requirements, we set our HQFmax specification at -80 dBm for eSI-G1 (first-generation eSI product) and at -90 dBm for our eSI90 (second-generation eSI product).
HQF metrology, conducted at the substrate level, provides a reliable measure of the finished devices’ RF performance. It is now being used by Soitec to report the expected RF linearity performance of ICs manufactured with RF-SOI substrates.
As a solution addressing the current and next generation of RF standards, eSI SOI wafers are enabling this market by meeting some of the most difficult LTE and LTE Advanced linearity requirements. Soitec is able to provide its customers with the eSI SOI substrates that meet their desired level of RF performance.
The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide. However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo.
In part 1 of ASN’s coverage of the workshop (click here if you missed it), we took a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis. Here in part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.
All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).
Low Power SOC design with RF circuit by the FD-SOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Corporation
This presentation details Sony’s work on an 28nm FD-SOI version of its CXD5600GF Global Navigation Satellite System receiver LSI for smartphones and mobile products. When the bulk version was first released in 2013, the 10mW power consumption made it the industry’s lowest. Now, with the 28nm FD-SOI version, they’ve gotten that down to a staggering 1mW – suitable for wearables. The presentation leads off by answering the question: Why FD-SOI? Sony engineers set themselves the challenge of a 0.6V target supply voltage for all logic, SRAM and analog (down from 1.1V in the previous generation). FD-SOI, especially leveraging body biasing, would enable them to attain this goal, providing a wide range of options for optimizing speed, power and area. The various steps and TEGs (test element groups) are detailed in this presentation, and compared with 28nm and 40nm bulk. The advantages for low-power RF were particularly compelling. This presentation has generated enormous attention in the press and in social media. For example, a week after EETimes published Sony Joins FD-SOI Club, it had been shared almost 200 times on LinkedIn.
Creation of high performance IP for FD-SOI by Kevin Yee, Director of Marketing, Cadence
As noted in this presentation, Cadence has existing solutions for 28nm FD-SOI, 14nm FD-SOI and 14nm FinFET-SOI. They have provided full design enablement for ST and Samsung processes. This presentation shows several examples of IP.
28nm FD-SOI Design/IP Infrastructure by Shirley Jin, Sr. Director of Engineering, VeriSilicon
Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. This presentation presents extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.
Designing with FD-SOI – Benefits and Challenges by Huzefa Cutlerywala, Sr. Dir. Technical Solutions, Open-Silicon
Open-Silicon is a leader in traditional ASIC solutions, derivative and platform SoCs, hardware and software design and production handoffs. They are a channel partner for ST’s FD-SOI in Japan, have pipe-clean design flows for FD-SOI, and are currently taping out an FD-SOI test chip for a customer. They see FD-SOI as ideal for consumer and networking/telecom/storage/compute applications. This presention lists what they see as the benefits (which are impressive) and challenges (which are fairly minor), and provides some details on GPU and DSP cores.
Ultra Low Power Memory Solutions for FD-SOI by Paul Wells, CEO, SureCore
SureCore develops ultra-low power embedded SRAM IP. Making the point that memory typically dominates SoC area and can consume 70% of the power, SureCore sees FD-SOI as an elegant solution. Working samples of their SRAM solution in ST’s 28nm FD-SOI were received in March 2014, showing a 50% dynamic power savings, and high performance at low operating voltage. Extensive comparisons are given in this presentation.
Synopsys FD-SOI IP Solutions by Mike McAweeney, Sr. Director, IP Product Sales, Synopsys
This presentation gives quite a detailed rundown of the ST-Synopsys 28FD-SOI IP program. Synopsys licenses a comprehensive, silicon-validated 28nm FD-SOI IP portfolio to Samsung’s foundry customers and other manufacturing partners. FD-SOI customers contract with Synopsys for standard Synopsys IP titles, with Synopsys customer support, part numbers, documentation and standard views. Slides 7 and 8 detail the commonly used interface, analog and display IPs available through Synopsys.
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The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)
In a SemiEngineering piece entitled FD-SOI meets the IoT, Executive Editor Ann Steffora Mutschler talked to a couple of design houses working on FD-SOI IoT projects. Synapse Design has taped out multiple chips, and has more projects underway, they told her, with reports of impressive power savings. In close collaboration with a foundry, OpenSilicon is working on an FD-SOI test chip that should tape out soon. STMicroelectronics indicates that silicon-proven IP is now available through a reseller/IP vendor, and that digital-analog integration benefits are especially compelling. Mutschler also talked to Sonics, Semico, and the big EDA players. (Click here to read the article.)
The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.
SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.
How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit. That’s for 2G, 3G and now 4G and LTE.
But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.
Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.
But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.
Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).
The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).
So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.
Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.
To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.
The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.
When it comes to next-gen mobile design, innovation really does start at the substrate level.
A new EETimes article entitled Sony Joins FD-SOI Club by Chief International Correspondent Junko Yoshida has created a tremendous buzz (click here to read it). The piece covers Sony’s presentation at the latest RF/FD-SOI workshop in Tokyo (many of the presentation are now posted here). Sony described their design experience with porting a GPS chip to 28nm FD-SOI, which resulted in a whopping 10x power reduction, down to just 1mW. Already the world’s smallest, lowest-power chip, the move to FD-SOI gives it a huge edge in mobile IoT and wearables, where battery life is critical. The response to the EETimes article was phenomenal. Within the first couple of days, it already had been shared over 90 times on LinkedIn and 50 on Facebook and Twitter.
|A very successful international workshop on RF-SOI was held in Shanghai earlier this fall. Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.
The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. , a spin-off company from SIMIT, and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.
Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)
This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.
Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006. He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)
Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)
Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.
Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.
Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates. They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate. (Click here to view the UCL presentation, and here to view the Soitec presentation.)
James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices. (Click here to view the presentation.)
Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)
The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates. Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.
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Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original here. Many thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.