An IBM paper on a 14nm SOI-FinFET SRAM functional down to 0.3V has garnered press attention. The paper, entitled 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation by R.V. Joshi et al, was presented during the Symposium on VLSI Circuits in Kyoto, Japan in June. According to the abstract, the authors presented a new, “… dynamic supply and interconnect boosting techniques for low voltage SRAMs and logic in deep 14nm FinFET technologies. The capacitive coupling in a FinFET device is used to dynamically boost the virtual logic and array supply voltage, improving Vmin. Hardware measurements show a 2.5-3x access time improvement at lower voltages and a functional Vmin down to 0.3V. Results are supported by novel physics-based capacitance extraction and novel superfast statistical circuit simulations.” EETimes reported on the paper in a piece entitled “IBM Slashes Next-Gen Power” (see it here), wherein the lead author confirmed that this work was based on a 14nm SOI-FinFET architecture.
It’s happening! GlobalFoundries is having an FD-SOI technical webinar on the 24th of June 2015. Don’t wait – sign up now – click here to get the registration document.
Here’s the information we know so far.
Title: Extending Moore’s Law with FD-SOI Technology
When: June 24, 2015, 10:00 am Pacific Time
Speaker: Jamie Schaeffer, Ph.D., FDSOI Product Line Manager, GLOBALFOUNDRIES
Where: a computer or mobile device near you!
Jamie Shaeffer’s been on the front lines of FD-SOI in recent days. In case you missed ASN’s recap of EDPS coverage (you can still read it here), he was on the panel discussion, agreeing that FinFET and FD-SOI can and will co-exist. His comment (as noted by Richard Goering of Cadence) really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
Also noted by Richard, Jamie was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
So while we’re waiting for “The Big GF FD-SOI Announcement”, we have a growing body of reports from industry events. In a SemiWiki blog (read it here), for example, Scotten Jones reported that GF’s Thomas Caulfield said that they are “…developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs.”
At DAC 52, GF’s Tim Dry gave what was reported to be a very well-attended presentation at the Synopsys booth. You don’t see the GF logo on the slides yet – but the source looks pretty clear….
His presentation was entitled Driving Innovation to Enable IoT Growth. Here’s a few snapshots of slides he showed.
Consider a ubiquitous security camera – a prime IoT sort of app. Here’s what FD-SOI does for it:
And then there’s the Smart Watch. 28nm FD-SOI with Forward Body Bias gives you great performance and over a week more of battery life than FinFET. Yes, please!
Next he looks at various applications, and the process technology needed to meet their power and performance requirements. As seen below, 55/40/28ULP and 28SLP each cover a limited segment of the range:
To cover the full range of requirements from low static power with RF to high performance active power, as seen below, you need 28FDSOI:
Recapping the presentation title, we see FD-SOI is the IoT growth enabler, as shown below:
Clearly GF’s rolling with this. So will you be at their FDSOI webinar on June 24? Of course you will. See you there!
Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.
Is there a place for FinFETs? Of course there is. If it’s a really big digital chip – no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.
But is that really where most designs are?
If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.
Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.
Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.
The session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.
And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”
In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:
The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
There you have it!
Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).
Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.
So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.
ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.
Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?
Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.
ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?
ASN: At what point in the design process do you typically come in? What sorts of services do you offer?
SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.
ASN: What do you see as the advantages of FD-SOI?
SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.
We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.
ASN: Designers of what kinds of chips should be thinking about FD-SOI?
SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.
ASN: Why do they ultimately choose it? Why do they hesitate?
SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.
ASN: Are there special considerations designers should think about before starting a project in FD-SOI?
SB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.
ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?
SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.
Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.
ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?
SB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market
ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?
SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.
ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?
SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.
We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.
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Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.
In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). While the first half addresses 14nm FinFET, starting at the 2:25 mark, it’s all about FD-SOI.
First Kelvin reminds viewers that 28nm will be a long-lived node thanks to its lower costs and the fact that it doesn’t use double patterning. He says Samsung has acquired a number of customers for FD-SOI, and now has the complete ecosystem to support the process technology, from substrate suppliers through the design chain. The key value, he says, is in the extremely low power operation and the low power supply voltage, which translates into long battery life for IoT and wearables. He also says he’s very excited by the prospects for FD-SOI in the automotive domain, where it is especially valued for its enhanced reliability.
The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers.
Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and invited talks on three main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. With its 40-year history, the SOI segment continues as world’s premier conference to present and discuss state of the art SOI technical papers.
There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure). The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies). More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families. Following a rush of activity about 10 years ago there was a dip, but activity over the last couple of years has once again been very strong.
The report provides a comprehensive overview, essential patent data for fully depleted SOI, plus a searchable database with links. It identifies more than 30 patent holders of FD-SOI related intellectual property, providing in-depth analysis of key technology segments and key players. “The major proponents of the FD-SOI technology have strong IP arms, but other unexpected players known as not supporting FDSOI [including TSMC and Intel] are also present,” notes the report.