Tag Archive FinFET

IBM 0.3V SOI-FinFET SRAM paper garners press attention

An IBM paper on a 14nm SOI-FinFET SRAM functional down to 0.3V has garnered press attention. The paper, entitled 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation by R.V. Joshi et al, was presented during the Symposium on VLSI Circuits in Kyoto, Japan in June. According to the abstract, the authors presented a new, “… dynamic supply and interconnect boosting techniques for low voltage SRAMs and logic in deep 14nm FinFET technologies. The capacitive coupling in a FinFET device is used to dynamically boost the virtual logic and array supply voltage, improving Vmin. Hardware measurements show a 2.5-3x access time improvement at lower voltages and a functional Vmin down to 0.3V. Results are supported by novel physics-based capacitance extraction and novel superfast statistical circuit simulations.” EETimes reported on the paper in a piece entitled “IBM Slashes Next-Gen Power” (see it here), wherein the lead author confirmed that this work was based on a 14nm SOI-FinFET architecture.

GlobalFoundries FD-SOI Webinar 24 June 2015, 10am PST: Be There!

It’s happening! GlobalFoundries is having an FD-SOI technical webinar on the 24th of June 2015. Don’t wait – sign up now – click here to get the registration document.

Here’s the information we know so far.

Title: Extending Moore’s Law with FD-SOI Technology 

Agenda:

  • FD-SOI technology overview
  • Power Performance Area (PPA) advantages
  • Transistor control with forward/reverse body biasing
  • The future of Moore’s Law with FD-SOI

When: June 24, 2015, 10:00 am Pacific Time

Speaker: Jamie Schaeffer, Ph.D., FDSOI Product Line Manager, GLOBALFOUNDRIES

Where: a computer or mobile device near you!

GF_DAC52_FDSOIwebinar_loresIn fact, GF made a point of inviting the crowd at the recent DAC 52 in San Francisco.

Jamie Shaeffer’s been on the front lines of FD-SOI in recent days. In case you missed ASN’s recap of EDPS coverage (you can still read it here), he was on the panel discussion, agreeing that FinFET and FD-SOI can and will co-exist. His comment (as noted by Richard Goering of Cadence) really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”

Also noted by Richard, Jamie was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.

So while we’re waiting for “The Big GF FD-SOI Announcement”, we have a growing body of reports from industry events. In a SemiWiki blog (read it here), for example, Scotten Jones reported that GF’s Thomas Caulfield said that they are “…developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs.”

At DAC 52, GF’s Tim Dry gave what was reported to be a very well-attended presentation at the Synopsys booth. You don’t see the GF logo on the slides yet – but the source looks pretty clear….

His presentation was entitled Driving Innovation to Enable IoT Growth. Here’s a few snapshots of slides he showed.

Consider a ubiquitous security camera – a prime IoT sort of app. Here’s what FD-SOI does for it:

GF_IoT_FDSOIsecuritycamera_image5lores

From GlobalFoundries presentation on Synopsys’ DAC52 stand.

 

And then there’s the Smart Watch. 28nm FD-SOI with Forward Body Bias gives you great performance and over a week more of battery life than FinFET. Yes, please!

GF_FDSOIsmartwatchDAC52image6lowres

From GlobalFoundries presentation on Synopsys’ DAC52 stand.

 

Next he looks at various applications, and the process technology needed to meet their power and performance requirements. As seen below, 55/40/28ULP and 28SLP each cover a limited segment of the range:

GF_IoTnodes2image9lores

From GlobalFoundries presentation on Synopsys’ DAC52 stand.

 

To cover the full range of requirements from low static power with RF to high performance active power, as seen below, you need 28FDSOI:

GF_FDSOIrangeIoTimage10lores

From GlobalFoundries presentation on Synopsys’ DAC52 stand.

 

Recapping the presentation title, we see FD-SOI is the IoT growth enabler, as shown below:

GF_FDSOI_IoTgrowth_image11lores

From GlobalFoundries presentation on Synopsys’ DAC52 stand.

 

Clearly GF’s rolling with this. So will you be at their FDSOI webinar on June 24? Of course you will. See you there!

FinFET or FD-SOI? Designers have a real choice, say experts

Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.

Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.

But is that really where most designs are?

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.

Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.

EDA experts weigh in at EDPS

Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.

EDPSlogoThe session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.

And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”

EDPS_FF_FDSOI_panel

EDPS 2015 panelists debate FinFET vs. FD-SOI. (Left to right: Marco Brambilla (Synapse Design); Kelvin Low (Samsung); Boris Murmann (Stanford); Jamie Schaeffer (GlobalFoundries). (Image courtesy: Richard Goering and Cadence)

In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:

  • Kelvin Low, Sr. Director Foundry Marketing for Samsung
  • Boris Murmann, Stanford professor and analog/mixed-signal expert
  • Marco Brambilla, Director of Engineering at Synapse Design
  • Jamie Schaeffer, Product Line Manager at GlobalFoundries

The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”

There you have it!

Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.

Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).

Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.

So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.

 

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

SatishBagalkotkar_outside

Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.

ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.

Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?

Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.

ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?

SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.synapse_logo_300_ppi

ASN: At what point in the design process do you typically come in? What sorts of services do you offer?

SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.

ASN: What do you see as the advantages of FD-SOI?

SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.

SynapseDesign_FDSOI_v_bulk

An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.

We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.

ASN: Designers of what kinds of chips should be thinking about FD-SOI?

SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.

ASN: Why do they ultimately choose it? Why do they hesitate?

SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.

ASN: Are there special considerations designers should think about before starting a project in FD-SOI?

SynapseDesign_FDSOI_diffSB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.

ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?

SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.

Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.

ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?

SynapseDesign_FDSOI_summarySB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market

ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?

SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.

ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?

SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.

We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.

~ ~ ~

Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.

Samsung/ChipEstimate video gives strong plug for FD-SOI

In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). While the first half addresses 14nm FinFET, starting at the 2:25 mark, it’s all about FD-SOI.

SamsungCDN

Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI in a CDNLive interview with ChipEstimate.TV’s Sean O’Kane.

First Kelvin reminds viewers that 28nm will be a long-lived node thanks to its lower costs and the fact that it doesn’t use double patterning. He says Samsung has acquired a number of customers for FD-SOI, and now has the complete ecosystem to support the process technology, from substrate suppliers through the design chain. The key value, he says, is in the extremely low power operation and the low power supply voltage, which translates into long battery life for IoT and wearables. He also says he’s very excited by the prospects for FD-SOI in the automotive domain, where it is especially valued for its enhanced reliability.

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

~ ~ ~

This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

IEEE SOI-3D-Substhreshold (S3S) Conference Issues Call for Papers

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers.

Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and invited talks on three main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. With its 40-year history, the SOI segment continues as world’s premier conference to present and discuss state of the art SOI technical papers.

The 2014 edition was a great success (click here to read about it).  The deadline for submissions for the 2015 conference is April 15, 2015 (click here for complete submission information).

Strong uptick in FD-SOI patent activity, according to KnowMade report

There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure).  The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies).  More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families.  Following a rush of activity about 10 years ago there was a dip, but activity over the last couple of years has once again been very strong.

The report provides a comprehensive overview, essential patent data for fully depleted SOI, plus a searchable database with links.  It identifies more than 30 patent holders of FD-SOI related intellectual property, providing in-depth analysis of key technology segments and key players. “The major proponents of the FD-SOI technology have strong IP arms, but other unexpected players known as not supporting FDSOI [including TSMC and Intel] are also present,” notes the report.

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

iedm_logoBeyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 2 of ASN’s IEDM coverage, we’ll cover future device architectures. In Part 1, we had a rundown of the top SOI-based advanced CMOS papers. In Part 3 we’ll look at MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

16.2: Dual-Channel CMOS Co-Integration with Si Channel NFET and Strained-SiGe Channel PFET in Nanowire Device Architecture Featuring 15nm Gate Length

P. Nguyen et al (Leti, ST, Soitec)

 

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM 14, Paper 16.2)

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM
14, Paper 16.2)

The researchers have fabricated the first hybrid channel omega-gate CMOS nanowire (NW) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FET. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NW (LG=15 nm) with +90% ION current improvement. [110]-oriented NW is shown to be the best candidate to improve drive current under compressive strain. In this work, the strain is measured by using precession electron diffraction with a 1nm spatial resolution. Furthermore, they show that hybrid integration reduces the delay of CMOS ring oscillator (FO=3) by 50% at VDD=0.9V. Finally, they demonstrate the most aggressively scaled hybrid CMOS NWs reported to date with NW width and gate length down to 7nm and 11nm, while maintaining high drive current (687µA/µm for p-FET and 647µA/µm for n-FET) with low leakage current and excellent short-channel-control (DIBL<50mV/V).

 

20.5: Study of the Piezoresistive Properties of NMOS and PMOS Omega-Gate SOI Nanowire Transistors: Scalability Effects and High Stress Level

J. Pelloux-Prayer et al (Leti, Soitec, Tokyo Tech)

The researchers present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). They show that the downscaling of geometrical parameters doesn’t allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.

 

20.3: Direct Observation of Self-heating in III-V Gate-all-around Nanowire MOSFETs

S.H. Shin et al (Purdue U)

Multi-gate devices, such as, FinFET, Gate-all-around transistors (GAA-FET) improve 3D electrostatic control of the channel, but the corresponding increase in self-heating may compromise both performance and reliability. Although the self-heating effect (SHE) of FinFET appears significant, but tolerable, the same may not be true for GAA geometry, especially in quasi-ballistic regime where hot spots and non-classical heat-dissipation pathways may lead to localized damage. The existing reports of the SHE on the SOI, FinFET or GAA-FET have so far relied either on indirect electrical measurements with inherent temporal delays, or on optical infra-red (λ>1.5μm ) imaging that cannot resolve deep submicron features. As a result, it has so far been impossible to resolve the spatio-temporal features of SHE fully. In this paper, the researchers develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the local temperature rise of GAA-FET with different number of nanowires (NW)(ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW.

 

9.6: In-situ Doped and Tensilely Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828µA/µm, Ion/Ioff ~ 1×105, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement

I-H. Wong et al (Taiwan U)

In-situ CVD doping and laser annealing can reach [P] and tensile strain as high as 2×1020 cm-3 and 0.37%. Junctionless Ge gate-all-around nFETs with 9 nm-Wfin and 0.8 nm-EOT achieves the record high Ion of 828 µA/µm. The Ion enhancement of ~40% is achieved under the tensile strain of 0.25%.

 

27.6: Flexible High-performance Nonvolatile Memory by Transferring GAA Silicon Nanowire SONOS onto a Plastic Substrate

J.-M. Choi et al (KAIST, NASA)

Flexible nonvolatile memory is demonstrated with excellent memory properties comparable to the traditional wafer-based rigid type of memory. This  achievement is realized through the transfer of an ultrathin film consisting of single crystalline silicon nanowire (SiNW) gate-all-around (GAA) SONOS memory devices onto a plastic substrate from a host silicon wafer.

13.2: High Ion/Ioff Ge-source Ultrathin Body Strained-SOI Tunnel FETs – Impact of Channel Strain, MOS Interfaces and Back Gate on the Electrical Properties

M. Kim et al (U Tokyo)

The researchers demonstrated Ge/strained-Si hetero-junction TFETs with in-situ B doped Ge. The increase in channel strain and optimization of PMA have successfully realized high performance of steep SSmin below 30 mV/dec and large Ion/Ioff ratio over 3×107.

13.3: Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective

Q. Huang et al (Peking U)

In this paper, a novel TFET design, called Pocket-mSTFET, is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from a circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated Pocket-mSTFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Circuit-level implementation based on Pocket-mSTFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

13.4: A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

J. Zhang et al (EPFL)

The researchers demonstrate a steep subthreshold slope silicon FinFET with Schottky source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA/μm is also achieved with high Ion/Ioff ratio of 107.

 

26.2: Thin-Film Heterojunction Field-Effect Transistors for Ultimate Voltage Scaling and Low-Temperature Large-Area Fabrication of Active-Matrix Backplanes

B. Hekmatshoar et al (IBM)

Heterojunction field-effect thin-film transistors with crystalline Si channels and gate regions comprised of hydrogenated amorphous silicon or organic materials are demonstrated. The HJFET devices are processed at 200ºC and room temperature, respectively; and exhibit operation voltages below 1V, subthreshold slopes of 70-100mV/dec and off currents as low as 25 fA/um.

 

26.7 Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel for 3D IC Applications

Y.-C. Cheng et al (National Tsing Hua U, National Chiao Tung U)

The hybrid fin poly-Si channel junctionless field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of steep SS (64mV/dec), high Ion/Ioff (>107) and small DIBL (3mV/V). The devices are highly promising for future further scaling and 3D stacked ICs applications.

 

35.1: A Physics-based Compact Model for FETs from Diffusive to Ballistic Carrier Transport Regimes

S. Rakhejaet al (MIT, Purdue U)

The virtual source (VS) model provides a simple, physical description of transistors that operate in the quasi-ballistic regime. Through comparisons to measured data, key device parameters can be extracted. The VS model suffers from three limitations: i) it is restricted to short channels, ii) the transition between linear and saturation regions is treated empirically, and iii) the injection velocity cannot be predicted, it must be extracted by fitting the model to measured data. This paper discusses a new model, which uses only a few physical parameters and is fully consistent with the VS model. The new model: i) describes both short and long channel devices, ii) provides a description of the current at any drain voltage without empirical fitting, and iii) predicts the injection velocity (device on-current). The accuracy of the model is demonstrated by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

 

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This is the 2nd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

 

10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

iedm_logoFD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we have a rundown of the top SOI-based advanced CMOS papers. In Part 2, we’ll cover papers on future device architectures. In Part 3 we’ll look at the papers on MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

 

The FD-SOI Papers

9.1: FD-SOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node.

Q. Liu et al (STMicroelectronics, CEA-LETI, IBM, Soitec)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In this work, researchers from STMicroelectronics and the IBM Technology Development Alliance demonstrate the successful implementation of strained FDSOI devices with LG, spacer & BOX dimensions scaled to 10nm feature sizes.

Two additional enabling elements for scaling FD-SOI devices to the 10nm node are reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 µA/µm for NFET at Ioff=1 nA/um (the highest performing FD-SOI NFET ever reported), and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 µA/µm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL are also reported.

 

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14. (Courtesy: ST et al, IEDM 2014)

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14.
(Courtesy: ST et al, IEDM 2014)

7.2: A Mobility Enhancement Strategy for sub-14nm Power-efficient FDSOI Technologies

B. De Salvo et al. (Leti, ST, IMEP, IBM, Soitec)

This paper presents an original multi-level evaluation methodology for stress engineering device design of next-generation power-efficient devices. Ring oscillator simulations showed that a dynamic power gain of 50% could be achieved while maintaining circuit frequency performance thanks to the use of efficient mobility boosters. Thus a clear scaling path to achieve high-mobility, power-efficient sub-14nm FDSOI technologies has been identified.

 

3.4: Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-Voltage Range SRAM Operation in 28nm UTBB FD-SOI

O. Thomas et al (UC Berkeley, ST)

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than 100fA/bitcell are measured in a 140kb programmable dynamic SRAM. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

 

27.5: New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration

C. Fenouillet-Beranger et al (Leti, ST, LASSE)

For the first time the maximum thermal budget of in-situ doped source/drain state-of-the-art FD-SOI bottom MOSFET transistors is quantified to ensure transistors stability in Monolithic 3D (M3D) integration. Thanks to silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Thanks to in-depth morphological and electrical characterizations, it shows very promising results for high performance Monolithic 3D integration.

 

9.2 Future Challenges and opportunities for Heterogeneous process technology. Toward the thin films, Zero intrinsic Variabiliiy devices, Zero power Era (Invited)

S. Deleonibus et al (Leti)

By 2025, 25 % of the World Gross Domestic Product will depend on the development of Information and Communication Technologies . Less greedy device, interconnect, computing technologies and architectures are essential to aim at x1000 less power consumption.

IBM’s SOI-FinFET, eDRAM and 3D Papers

32.1: Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme

H. Tsai et al (IBM)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision. In this paper, IBM researchers present the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node.

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

 

Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

 

3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News)

C-H. Lin et al (IBM)

The IBM team presents a fully integrated 14nm CMOS technology featuring FinFET architecture on an SOI substrate for a diverse set of SoC applications including high-performance server microprocessors and low-power ASICs. A unique dual workfunction process optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel and without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. Because the technology is envisioned for use in SoC applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom than ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

The SOI FinFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

 

16.1: First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications

P. Hashemi et al (IBM)

Strained SiGe FinFETs are a promising PMOS technology for the 10nm technology node and beyond, due to their excellent electrostatics and built-in uniaxial compression. Yet while SiGe FinFETs with moderate germanium (Ge) content have been characterized, little data exists on FinFETs with high Ge  content. And, what little data does exist is mostly focused on relaxed or strained pure Ge. For the first time anywhere, IBM detailed CMOS-compatible, low-power and high-performance SiGe PMOS FinFETs with more than 50% Ge content. The devices feature ultra-narrow fin widths – down to 3.3 nm – which provide excellent short-channel control for low-power applications.  Using a Si-cap-free passivation process, they report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1e13 cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. They demonstrated the highest performance ever reported (Ion=0.42mA/µm and Ioff=100nA/µm) for sub-20nm PMOS FinFETs at 0.5 V.

 

19.4: 0.026µm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications

C. Pei et al (IBM)

This paper presents the industry’s smallest eDRAM based on IBM’s 22nm (partially depleted) SOI technology, which has been recently leveraged for IBM’s 12-core 649mm2 Server Processor POWER8™. It summarizes the n-band resistance innovations, and reports for the first time the asymmetric embedded stressor, cavity implant and through gate implant employed in 22nm eDRAM technology. The fully integrated 256Mb product array has demonstrated capability of 1.4ns cycle time, which is significantly faster than any other embedded DRAM.

 

14.6: Through Silicon Via (TSV) Effects on Devices in Close Proximity– the Role of Mobile Ion Penetration – Characterization and Mitigation

C. Kothandaraman et al (IBM)

The research team identified and studied a new interaction between TSV processes and devices in close proximity, different from mechanical stress. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. They then presented an improved process, confirmed in test structures and DRAM.

 

RF-SOI

18.4: Technology Pathfinders for Low Cost and Highly Integrated RF Front End Modules

C. Raynaud (Leti)

This paper highlights the challenges related to the increasing number of modes (GSM, WCDMA, LTE) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multimode multi–band RF Front End modules.

 

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This is the 1st post in a 3-part series. Part 2 (click here to  read it) of ASN’s IEDM ’14 coverage looks at papers covering SOI-based future device architectures.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.