Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Key takeaway #2: If you need a Goldilocks process node – where you’ll get just the right balance between active power, unit cost and investment – look to FD-SOI. And, btw, the IP landscape has improved dramatically. Those were just some of the great points made by Huibert Verhoeven (shown above), GM/SVP of Synaptics’ IoT Division in his talk at the recent SOI Symposium in Silicon Valley.
BTW, if you missed part 1 of our coverage —Silicon Valley SOI Symposium a Huge Success. Key Takeaways (Part 1) Here. – you’ll want to be sure to read it, too. Almost all of the presentations are now posted on our website – click here to access them.
In this post here, we’ll cover presentations by Synaptics, GlobalFoundries, STMicroelectronics, Anokiwave and Dolphin Integration. It was a really full, day, so be sure to stay turned for Part 3 of our coverage to follow shortly: it will highlight the remaining presentations and panel discussions.
Synaptics’ Verhoeven’s presentation Revolutionizing User Experience Through Secure Neural Network Acceleration at the Edge was about Smart Home and using SOI. Synaptics is a human interface (HMI) company that’s been doing neural networks since 1986. They’ve always been on the leading edge, from their first shipment of PC touchpads to becoming a dominant force in all things HMI today: they now ship over a billion units annually.
They currently have SOI products shipping with dedicated neural networks for voice, he said. European [privacy] regulations have played a part in driving their use of SOI, as have challenges regarding power and heat. Things are getting smarter at the edge. For example, not only do users want their coffee machine to offer the usual morning espresso, Synaptics says that the next step is for your coffee machine to recognize you’re looking extra tired and ask if you might want a double?!
For them Smart Home and multi-modal applications are the primary area of interest, as well as some automotive. Although their biggest customers have resources, others need guidance. Voice is a critical component, but now you also need video and display.
Why SOI? Their HMI vision requires low power, significant computation and dedicated neural network hardware, explained Verhoeven, so FD-SOI with RF meets their needs. “22nm SOI is a Goldilocks IoT Process Node,” he proclaimed. It gets the combination of active power, unit cost and investment just right. What’s more, he said, “The IP landscape has improved dramatically. Our choice of SOI was not an accident.” Be on the lookout for more products leveraging FD-SOI over the next six months, he concluded.
At this point on SOI, they’ve got 1 TOPS products with dedicated NPU for speakers, soundbars, Wi-Fi mesh, appliances, STBs and smart displays. These products have voice and sensor real-time (RT) AI. Next up is >4 TOPS on SOI with dedicated NPU, targeting STBs and smart displays with voice, video, imaging and RT AI.
“Our clients are at the forefront of changing the world,” declared Mark Granger, VP of the Automotive Product Line at GlobalFoundries. His presentation, Capturing High Growth Market Opportunities with SOI, detailed how mobility, automotive and IoT are the growth markets for SOI. So not unsurprisingly, GF’s 22nm FD-SOI technology, 22FDX, is seeing particular traction in mobile, edge, wearables and automotive.
They’ve got twice as many tape-outs this year as they did a year ago, he noted. GF’s SOI portfolio includes 22FDX®, 45RFSOI and 8SW/7SW RF SOI for 5G/mobility; 22FDX for automotive (fully qualified for automotive Grade 2, with Grade 1 on the way); and 22FDX, 130RFSOI and 8SW/7SW RF SOI for IoT.
GF has announced a stream of good news recently:
You might have heard about the Dolphin Integration news, as we covered it recently here at ASN (if not, be sure to read it here). Dolphin’s IP and methodology solutions address energy efficiency challenges. Automated transistor body biasing adjustment can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. At the Silicon Valley event, Dolphin Integration CEO Philippe Berger provided additional information in his talk, FD-SOI IP Platform for Energy-Efficient IoT SoC.
In another GF-related talk, Nitin Jain, the CTO of longtime GF RF-SOI customer Anokiwave presented Unleashing the mmWave Phase Array Using SOI for 5G & Satcom. Anokiwave is a fabless semi IC company (you’ll find a good technical discussion of mmWave phase array written by their Chief Architect here). They do active antennas (aka phased array), something the military’s done for a long time, but now Anokiwave is bringing it to new markets and applications including radar, satcom and 5G. What they’ve been able to do is planarize the active antennas. They use GF’s 45RFSOI process technology for phased array systems because of the cost, performance, scalability and system enhancements it enables. 45RFSOI, he explained, is ideal for beam-forming FEMs (including the switches, LNAs and PAs). The move to 5G/mmWave is going to require a lot of antennas, so these Anokiwave ICs are headed to high volumes, concluded Jain.
As Roger Forchhammer, Director of Business Development at STMicroelectronics pointed out in his presentation, Automotive FD-SOI Microcontrollers with Embedded PCM, ST pioneered FD-SOI (and that was almost a decade ago, btw). Then in February 2019, they announced a world first: they’d begun sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on embedded Phase-Change Memory (ePCM) to 10 alpha customers. These MCUs target powertrain systems, advanced and secure gateways, safety/ADAS applications, and vehicle electrification.
(In case you want technical details, the breakthrough ePCM eNVM was first presented at IEDM in December 2018 – you can get the presentation that accompanied the paper, Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller Applications embedding 16MB Phase Change Memory, from the ST website.)
In his Silicon Valley presentation, Forchhammer said they’re now doing Stellar, a whole family of automotive products on FD-SOI. To do it, they’d taken an existing device and moved it to 28nm FD-SOI with ePCM, which they manufacture at their fab in Crolles, France. A major advantage for automotive he cites is that in software updates it’s bit-level programmable. “ST is fully behind FD-SOI,” he concluded, adding that we’re see more automotive as well as IoT products coming soon.
Well folks, that’s all for this post. We’ll finish up our coverage of the SOI Consortium’s 2019 Silicon Valley Symposium in the next ASN post (there was so much to cover!). So please stay tuned.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
GF’s 22FDX® (22nm FD-SOI) offering is on an automotive roll. The technology platform has been certified for several key automotive standards, and GF has announced an exciting new ADAS customer in Arbe Robotics.
In addition to sharing info from various press releases and blogs, ASN also had a chance to catch up with Mark Granger, GF’s VP for automotive, who provided some great insights. Read on!
When it comes to compliance, automotive industry standards are excruciatingly rigorous. Every part that goes into a car must adhere to the relevant standards: chips are no exception. One such standard is the AEC – Q100, a “Failure Mechanism Based Stress Test Qualification For Integrated Circuits”. The AEC – aka the Automotive Electronics Council – handles those testing standards and certification. Grade 2 means a technology is certified for the -40°C to +105°C ambient operating temperature range. To achieve Grade 2 certification, devices have to successfully withstand reliability stress tests for an extended period of time over the specified temperature range.
GF recently announced that 22FDX has been AEC Q100 Grade 2 certified (press release here). However Granger adds that for their customers, they’ve added additional headroom that takes them to 125°C. They’re now working on Grade 1 certification, he says, which means the devices are certified to handle junction temperatures up to 125°C (and there again, GF has added additional headroom that takes them to 150°C). That should be done by the end of 2018. The ability you get with FD-SOI to tune the transistors using body biasing is really beneficial here, he says.
For GF, the 22FDX qualifications exemplifies their commitment to providing high-performance, high-quality technology solutions for the automotive industry. The automotive industry is driven by a “zero excursions – zero defects” mindset, says Granger, and that drives the foundry, too.
SOI has been used for decades across industries where heat and electromagnetic radiation are challenges, bringing soft error rates (SER) down by orders of magnitude, notes Granger. (SOI, btw, essentially eliminates what are known as Single Event Upsets (SEU) caused by latch-up, which in turn brings down SER.) That in turn, ties into the FIT (failure in time) rate – and that’s part of the ISO 26262 “Road vehicles – Functional safety” standard – where 22FDX is also certified.
As a part of GF’s AutoPro™ platform, 22FDX allows customers to easily migrate their automotive microcontrollers and ASSPs to a more advanced technology, while leveraging the significant area, performance and energy efficiency benefits over competing technologies. Moreover, the optimized platform offers high performance RF and mmWave capabilities for automotive radar applications and supports implementation of logic, Flash, non-volatile memory (NVM) in MCUs and high voltage devices to meet the unique requirements of in-vehicle ICs.
GF’s Fab 1 in Dresden, Germany (which is where they do 22FDX) also has achieved ISO-9001/IATF-16949 certification, which demonstrates that it is capable of meeting the stringent and evolving needs of the automotive industry. (IATF is the International Automotive Task Force. 16949 is a Quality Management System (QMS) certification specifically for the automotive sector.)
Granger wrote a really informative blog on the GF website – you can read it here. It includes this graphic, indicating where in the car 22FDX-based parts are expected to go.
GF recently announced that Arbe Robotics selected 22FDX® as the process technology for its groundbreaking patented imaging radar. Arbe aims to achieve fully automated system capabilities and enable safer driving experiences for autonomous vehicles (read the press release here).
As the first company to demonstrate ultra-high-resolution at a wide field of view, Arbe Robotics’ radar technology can detect pedestrians and obstacles at a range of 300 meters, in any weather and lighting conditions. The processor creates a full 3D shape of the objects and their velocity, and classifies targets using their radar signature.
As Granger noted in his blog, “Radar is one of several sensor types used to detect objects near a vehicle, to enable features like adaptive cruise control. Lidar is another. It uses pulsed lasers to determine distance from an object by measuring the time it takes for the light to reflect back. However, lidar is currently expensive and is affected by weather conditions. Radar is less expensive, and higher-resolution radars promise to compete well with lidar in automotive applications, thereby enabling lower-priced vehicles to enjoy greater ADAS capabilities. 22FDX-based radar sensors can provide higher resolutions and less latency than current radar sensors at a very low total system cost.”
While they may be complementary at first, there is a battle brewing between high-resolution radar and lidar, Granger told ASN. Putting their solution on 22FDX enables Arbe to achieve a 77 GHz mmWave radar and compete cost-effectively with lidar. “They wanted the best,” says Granger. 22FDX can achieve the requisite Ft and Fmax figures of merit. And with transistor stacking, they can also integrate the power amplifier (PA) on a single device. With the low inherent capacitance of the PA in 22FDX, you can get the high power output you need for mmWave but with low power consumption.
GF blogger Dave Lammers has also written a great piece about the Arbe solution (you should read it: here’s the link). “The company said its advanced technology allows the detection of small targets, such as a human or a bike even if they are somewhat masked by a large object such as a truck,” he writes. “The imaging radar can determine whether objects are moving, and in what direction, and alert the car in real-time about a risk.
“While other car sensors can fail when it is raining, if there’s fog, and due to blinding lights such as a sudden reflection, Arbe’s radar is completely oblivious to all those factors. The custom designed radar processor creates a full real-time 4D image of the environment, and classifies targets using their radar signature.”
Avi Bauer, Arbe’s VP of R&D, is now clearly an SOI fan. Lammers quotes him as saying, “With SOI the design is more straightforward, and (voltage) biasing allows you to do things that cannot be done in standard CMOS. For the transmit and receive modules, SOI’s higher resistivity substrate benefits the passive components – inductors and capacitors – and allows good isolation. High Q passives are important. At 22nm, SOI allows better performance overall.”
Clearly good things are coming down the road for FD-SOI!
Some really innovative start-ups presented chips they’re doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We’ll cover those here in Part 3 of ASN’s coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who’s designing chips on FD-SOI, and VLSIresearch explained why. You can read that here.
Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
Ineda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They’re using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes.
In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud.
Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN’s coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor’s talked about their roadmap.
eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July ’18.
Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic.
Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec’s Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting.
In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers & acquisitions would not solve the problem, they’ve opened a second round, targeting another $160 billion.
China’s two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals.
IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said.
The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists.
QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you’ve got one set of IP, and you can decide at runtime where you’re going for low power or high performance. With a lot of power domains, you see the benefits at the system level.
GF VP Dave Eggleston said they’re seeing early adopters of eMRAM, especially for wearables with RF and low power.
ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores.
Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”.
It’s not too late for FD-SOI: it’s perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they’re happy to focus on companies still on the older nodes.
The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You’ve got more potential customers, and your volume runs can be bigger.
In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day’s three take-aways:
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
GlobalFoundries’ new ecosystem partner program, called RFwave™, aims to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks (read the full press release here). The program aims to give designers a low-risk, cost-effective path to highly optimized solutions that leverage GF’s platforms including RF on FD-SOI and RF-SOI. The target is wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.
As such, the RFwave™ partner program provides GF customers with IP design elements, EDA tools, design consultation and services and OSAT product packaging and test solutions. These products and services are validated, and comprise a plug-and-play catalog of design solutions. With this level of integration, GF customers can create high-performance designs while minimizing development costs.
Bami Bastani, senior vice president of GF’S RF Business Unit, says, “As a leader in RF, GF’s RFwave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.”
Initial members of the RFwave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.
Following the immense success of last year‘s FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up.
ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design.
You’ll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices.
Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond.
The design examples will cover basic building blocks through SoC implementations. A global Q&A session will close the day.
Here’s a little more info on how the day will unfold. Click on the slides to see them in full screen.
FDSOI-specific design techniques for analog, RF and mmW applications – Andreia Cathelin, Fellow, STMicroelectronics
Andreia Cathelin is ST’s key design scientist for all advanced CMOS technologies, and is arguably the world’s leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She’ll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance.
Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications – Frank Zhang, Principal Member of Technical Staff, GlobalFoundries
Frank Zhang has designed chips using GF’s 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements.
Energy-Efficient Design in FDSOI – Bora Nikolic, Professor, UC Berkeley
Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team’s RISC-V chip was cited as one of Dr. Cathelin’s “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He’ll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley’s latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI.
mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies – Sorin Voinigescu, Professor, University of Toronto
Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He’ll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he’ll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he’ll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies.
With over 100 attendees filling every chair in the auditorium, last year’s training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”
2018 will be no different – except that it’s sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks.
Here’s key info you need to sign up. See you there!
When: 27 April 2018, 7:30am – 5pm.
Where: Crowne Plaza San Jose, Milpitas CA (parking is free)
Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)
How to sign up: Click here to go directly to the registration site.
They’ve got initial silicon of Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology, and it’s got record power efficiency (read the full press release here). The chip offers high performance image acquisition and processing capabilities and supports AI / Neural Network (NN) vision operation with a total of 1 TOPS at 500 MHz on 4 parallel engines. With all functions including quad-core Arm® Cortex®-A53, Tensilica DSPs, and INVECAS’ LPDDR4-Interfaces activated, the SoC shows single digit power dissipation without the need for forced cooling, which is of significant importance for embedding in automotive environments.
Targeting automotive computer vision applications, the SoC was created in close cooperation with Arm, ArterisIP, Cadence, GF, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform, where about 40 partners in Europe cooperated to propel the FDSOI-Design Ecosystem.
Of particular importance is the new and reduced power footprint of this SoC in 22FDX-technology from GF. AI/NN-operation for image recognition is available today, but most of the solutions need active cooling. Implementation of Dream Chip Technologies’ SoC on GF’s 22FDX platform demonstrated single digit Watt and cooling targets for designers managing power dissipation. If needed, the SoC bears the potential to increase the performance even further up to 2 TOPS at 1.0 GHz by applying GLOBALFOUNDRIES’s forward body-bias capabilities and other optimization techniques.
The jointly developed ADAS SoC platform from Dream Chip Technologies is available now. Part of GF’s FDXcelerator™ Partner Program, Dream Chip is the largest independent German Design Service company specialized in the development of large ASICs, FPGAs, embedded software and systems with a strong application focus on automotive vision systems (ADAS).
FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read:
But, if you don’t have time to read them all right away, here are some highlights to tide you over til you do.
Ed Sperling at SemiEngineering sees FD-SOI adoption “… gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.”
After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won’t necessarily be the billions of units per chip needed to amortize exorbitant design costs.
In particular, for FD-SOI adoption he cites, “…the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF’s Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.)
ST’s Giorgio Cesana makes an interesting point about body biasing (that I hadn’t hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that’s not a problem after all.)
Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They’re looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that….
In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “…as new markets open up, chipmakers are finding themselves much closer to the application than in the past.”
All in all a great read – don’t miss it.
David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF’s Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF’s 22FDX (FD-SOI) technology at Mobile World Congress.
For example, Nanotel Technology is using 22FDX to “…reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company’s CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI.
Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There’s no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company’s CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM.
Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “…the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.”
Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia & Europe). The IP covers integrated baseband, power management, RF radio and front-end components.
Lammers also cited Anubhav Gupta, GF’s director of strategic marketing and business development for IoT, AI & Machine Learning. He said they’ve got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated.
In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech’s Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you’re looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.”
Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They’ll be in risk production in early 2019.
Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”.
All in all – products and press – it’s a really fine Q1.