Tag Archive GF

  • Home   /  
  • Posts tagged "GF"
    • ( Page2 ) ( Page2 )
ByAdele Hars
, , , , , ,

GF Delivering 45RFSOI Customer Prototypes for 5G

GlobalFoundries’ 45nm RF-SOI platform is qualified and ready for volume production on 300mm wafers (read the company’s full press release here).  It was just at the beginning of last year that GF announced the PDK availability for 45RFSOI (we covered it here).  Now there are several customers engaged for this advanced RF SOI process, which is targeted for 5G mmWave front-end module (FEM) applications, including smartphones and next-generation mmWave beamforming systems in future base stations.

In case you missed it, at the Consortium’s Shanghai symposium GF’s Mr. RF — Peter Rabbeni — gave a great talk on the company’s RF-SOI capabilities, which are very impressive (they’ve shipped over 32 billion RF-SOI devices, after all). His slides from that day are available here on the SOI Consortium website. See his slide 12 for an indication of how 45RFSOI fits into the overall picture.

Slide 12 from Peter Rabbeni’s talk at the RF-SOI Symposium in Shanghai. (Courtesy: GlobalFoundries and the SOI Consortium).

As they explain it, next-generation systems are moving to frequencies above 24GHz, so higher performance RF silicon solutions are required to exploit the large available bandwidth in the mmWave spectrum. GF’s 45RFSOI platform is optimized for beam forming FEMs, with features that improve RF performance through combining high-frequency transistors, high-resistivity SOI substrates and ultra-thick copper wiring. Moreover, the SOI technology enables easy integration of power amplifiers, switches, LNAs, phase shifters, up/down converters and VCO/PLLs that lowers cost, size and power compared to competing technologies targeting tomorrow’s multi-gigabit-per-second communication systems, including internet broadband satellite, smartphones and 5G infrastructure.

Psemi and Anokiwave are among those companies at the forefront of 45RFSOI use.  Citing the drive to deliver faster, higher-quality video, and multimedia content and services Anokiwave CEO Bob Donahue said, “GF’s RF SOI technology leadership and 45RFSOI platform enables Anokiwave to develop differentiated solutions designed to operate between the mmWave and sub-6GHz frequency band for high-speed wireless communications and networks.”

The production line is in East Fishkill, N.Y.

ByAdele Hars
, , , , , , , , , , , , ,

FD-SOI in China – Foundries See Interest Mounting Fast

The foundries sent their top guns to the FD-SOI Forums organized by the SOI Consortium and its members in Shanghai and Nanjing. This is a quick recap of what they said.

GF: Winning with SOI

“With FD-SOI, we can deliver a level of integration never before possible,” said GlobalFoundries CEO Sanjay Jah in his Shanghai talk, Winning With SOI. The ecosystem they’re building is covering both design and supply. He showed a video of the new fab, which is going up at an enormous speed in Chengdu, China. It’s huge: a half-kilometer long on one side. And it will start producing wafers in H218, ramping up to a million/year.

GlobalFoundries CEO Sanjay Jah citing key TAMs at the FD-SOI Forum in Shanghai. (Photo courtesy: SOI Consortium & GlobalFoundries)

FD-SOI is past the discovery phase now, he continued. They’ve got 135 engagements and 102 PDKs downloaded. In China alone, they have ten customers taping out 15 products. The key is going after high-growth markets, including mobility, IoT, RF/mmW and automotive (see picture above). “We see intelligence migrating to the edge,” he said.

With 22FDX®, there are 11 fewer mask steps than industry standard 28nm HKMG processes, he said. Back bias is a big differentiator, reaping benefits without penalties and shortening time-to-market. eMRAM is also a big driver of interest. The IP – both foundation and complex – is silicon-proven: you can measure it. The FDXceleratorTM program now has 35 partners.

He also touched on RF-SOI, where GF is #1 in terms of market share.

“I’m very excited about the future for us,” he concluded.

With back bias, you can do even more, said GF’s Sanjay Jha, so customers feel the risk is lower. (Photo courtesy: SOI Consortium & SOI Consortium)

In the Nanjing SOI forum, GF’s head of China sales, Zhi Yong Han gave an excellent presentation that is posted on the SOI Consortium website (you can get it here). He emphasized that they are educating designers to help them take advantage of the FD-SOI for advanced devices, as well and working with universities. The result is that they’re seeing significant growth in the Chinese market.

Slide 9 from GF’s Nanjing presentation shows all the boxes ticked: 22FDX® is qualified for volume production. (Courtesy: GlobalFoundries and the SOI Consortium)

Zhi Yong Han also highlighted the excellent performance of GF’s RF-SOI offering, and the huge capacity they’re building out. NB-IoT clients are now approaching them, he added.

Samsung: World’s 1st eMRAM Test Chip

“E.S. stands for Engineering Sample,” quipped Dr. E.S. Jung, EVP/GM of the foundry business for Samsung Electronics. A very energetic speaker, his talk covered Cutting Edge Technology from a Trusted Foundry. (Samsung Foundry is now a standalone business unit.)

Samsung has seven major 28nm FD-SOI customers, and has taped out over 40 products. This coming year a number of products will be taking off in mass production, he said.

eMRAM (which only required three additional mask steps) is the newest addition to the family of embedded non-volatile memories and it offers unprecedented speed, power and endurance advantages (see the press release here).

Regarding back bias in the IP, he said they’ve solved it working with their suppliers, EDA vendors and customers. Migrations will re-use that IP.

At the Nanjing SOI forum, VP of Samsung Foundry Suk Won Kim looked at design methodology in his talk, 28FDS Samsung Foundry Platform. It’s easy to implement your SoC with FD-SOI technology, he said, explaining how PPA and cost/transistor makes 28FDS an optimal node. The PDK – including RF – are ready for high volume production. There is no design overhead: the differences between FD-SOI and bulk are not difficulties, he emphasized.

For 28FDS, the full spectrum of the ecosystem is available: design enablement, advanced design methodologies, and silicon-proven IP. Samsung has a body bias generator, and the design methodology takes care of checking the body bias integrity. In terms of the physical design, there is awareness in the floorplan for body biasing and flip-well devices. In terms of timing sign-off, there’s almost no change – in fact there are fewer PVT corners. The flow for power integrity sign-off doesn’t change. The RTL-to-GDS flow is about the same – and where they diverge, designers are embracing the differences.

And for those looking ahead, the PDK for 18FDS evaluation will be available soon.

More pics?

For pics of many more slides, check out articles posted about the SOI forums in the China press, including EETimes China, EEFocus, and EDN China (plus see their focus piece).

BTW, there were five days of events in Shanghai and Nanjing, with over 50 presentations  given in ballrooms full-to-bursting. As noted in my previous post, China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth, many (but not all) of the presentations are now available  in the Events section here on the SOI Consortium website.

So in future posts, we’ll cover the EDA/IP companies, design tutorials and user presentations for both the FD-SOI and RF-SOI China events — including those not posted. Stay tuned!

ByAdele Hars
, , , , , , , , , , , , , , , , , ,

China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth

The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.

These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.

Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Sciences in Shanghai giving a keynote address at the 5th Shanghai FD-SOI Forum. (Photo courtesy: Simgui and the SOI Consortium)

Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:

(Photo credit: Adele Hars)

Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.

“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.

The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.

FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.

RF-SOI coverage included pieces in leading publications such as China IC, EETimes China, EDN China, EEFocus and SemiInsights.

ByAdele Hars
, , , , , , , , , ,

Synopsys-GF-Qualcomm Panel, Leti/Fraunhofer Team Up – FD-SOI Center Stage at Leti Innovation Days

Before summer’s no more than a twinkle in our eyes, let’s take a moment to catch up on a key event where FD-SOI took center stage: Leti Innovation Days. French research powerhouse Leti was celebrating 50 years of innovation, so it was a real gala event.

FD-SOI and other SOI technologies were seen and heard throughout the presentations and in the exhibition spaces. But there were a couple of things that were especially interesting that I’ll cover here in ASN. In particular, a panel discussion with GF, Synopsys and Qualcomm; and the big announcement from Leti and Fraunhofer supporting continued FD-SOI development.

(There were also some great info about body biasing in FD-SOI, but we’ll save that for a future post.)

The Panel & More

A session on Micro-nano Pathfinding and the Digital Revolution featured a fascinating panel discussion on Future Applications and New Technologies. As Rajesh Pankaj from Qualcomm, Alain Mutricy from GF and Antun Domic from Synopsys discussed the prospects, FD-SOI quickly took center stage.

FD-SOI took center stage at this Leti Innovation Days 2017 Panel Discussion. Left to right: Antun Domic, CTO, Synopsys; Alain Mutricy, GF’s SVP, Product Management Group; Rajesh Pankaj, Qualcomm’s SVP Corporate R&D.

Here are some FD-SOI observations from GF’s Alain Mutricy:

  • It’s planar, so it’s not hard to design in.

  • It’s the only technology that can get down to 0.4V, and it has the lowest leakage/cell. That will be key for all mainstream applications (except high-end servers) for at least a decade or two.

  • 12 FDX with forward body bias (FBB) will get 7nm FinFET performance.

  • They’re looking forward to broad FD-SOI adoption. It will enable the next wave of technology and mobile devices.

Synopsys’ Antun Domic noted that:

  • Currently, 50% of silicon area comes from just 3 or 4% of designs. FD-SOI makes design simpler, so the EDA companies are looking for it to open the door to more designs.

  • From a design perspective, three thresholds was standard, but that’s not enough. Place and route could stretch to 10 or 15 corners. FD-SOI simplifies tool flow and cuts mask costs. It’s less complicated than you think.

That tech session, btw, began with an excellent testimonial by Leti partner, Soitec. (Remember: the technological innovation that enabled modern SOI wafers came out of Leti and was industrialized by Soitec.) Check out the snapshot below to get an idea of all the areas that SOI-based technologies address.

Soitec SVP Christophe Maleville shows the many product lines of SOI substrates.

Leti, Fraunhofer & FD-SOI

The big piece of news to come out of Leti Days is that Leti is teaming up with Fraunhofer to “…strengthen microelectronics innovation in France and Germany” (read the press release here). The agreement was signed by Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner at an official ceremony. A lively the press conference followed. Prof. Lakner emphasized that they are working on a common European roadmap, with a clear plan for collaboration on FD-SOI. Europe, he said, is a good idea, and working together, France and Germany can do a lot for industry. For FD-SOI, Leti is focused on the front-end, and Fraunhofer is working on the back-end.

Working together, they can elevate pillars like FD-SOI from the country level to the European level, noted Dr. Semeria. And that puts them in a more elevated position for EC funding initiatives such as an upcoming IPCEI – which stands for Important Project of Common European Interest.

Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner announced “new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.” (photo credit: Pierre Jayet)

Initially, however, the focus will be on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in IoT, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries. A second phase extending to other partners and countries is possible. We’ll keep you posted.

In closing, I’m sure you’ll all join me in extending hearty congratulations to Leti on their 50th anniversary. And here’s to their next 50 years of innovation – can you imagine what that might bring? It rather boggles the mind, doesn’t it?

 

ByAdele Hars
, , , , ,

GF Triples FDXcelerator Partner Base in 1st Year

As of September 2017, GlobalFoundries’ FDXcelerator program now counts 21 members. Its purpose is to extend the reach of the FD-SOI ecosystem, creating an open framework that allows these selected partners to integrate their products or services into a validated, plug-and-play catalog of design solutions. The program was first launched with seven partners in September 2016 – so membership has already tripled in just one year.

As such, FDXcelerator delivers design elements (IP), platforms (ASIC), tools (EDA), reference solutions (reference designs, system IP), resources (design consultation, services), and product packaging and test (OSAT) solutions that enable GF’s customers to improve FD-SOI-based SoC development cycle times and minimize development costs.

The program was originally founded with Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services).

Partners that have joined since then include:

QuickLogic — mass production proven ultra-low power embedded FPGA; complete SW support for FPGA design and SoC integration in 22FDX ultra-low power embedded FPGA (eFPGA) Intellectual Property, complete software tools and a compiler (press release here).

ASE Group — advanced packaging, assembly and test development services. Chip scale package types to include: flip chip and wafer level Fan In and Fan Out.

Amkor Technology — advanced packaging, assembly and test development services. Package types to include flip chip, wafer level fan out and wire bond.

Infosys — Silicon-to-systems range of engineering services. Software services ranging from various firmware, embedded and applications-specific offerings.

Mentor Graphics — FDX-tailored Calibre™ solutions for timing and physical verification. Mentor ICD to support, floor planning, synthesis, place & route capabilities and Tessent™ suite to offer DFT flow support (press release here).

Rambus — Cryptofirewall cores that complement security implementations; DPA counter measure solution offerings to enhance security measures (press release here).

Sasken — Software solutions and processes for IoT, automotive and industrial and emerging device technologies. Offer turnkey solutions including hardware and software for complete SoC production.

Sonics — EPU™ Studio based on the Sonics ICE-GRAIN™ power architecture to support body-bias. Configurable on-chip network suite of offerings to support design of complex on-chip interconnects between cores (press release here).

Attopsemi — proprietary I-fuse™ OTP IP provides small size, high reliability, low program voltage, low power and wide temperature range to enable harsh applications such as automotive, 3D IC, and IoT applications (more here).

Fraunhofer IIS — applied research and development for ASIC, system-on-chip (SoC), and IP. Offers dynamic biasing IPs for advanced SoC designs in 22FDX technology.

Racyics — IP and design services for 22FDX process technology. “makeChip” design service platform provides an IT infrastructure with EDA tools and technology data setup (press release here).

Perceptia — all-digital PLL IP and complementary design solutions for 22FDX. Custom IC design and physical implementation services for GF FD-SOI process technologies (press release here).

eVaderis — optimized eNVM and processor subsystems IP for non-volatile IoT SoCs. Advanced IP for efficient code and data management in ultra-low power designs (press release here).

Uniquify — DDR Interface IP provides the right power, performance, area and reliability for FDX™-based SoCs in portable applications. Memory interface IP employs industry-leading adaptive technology, based on 14 issued patents, to deliver maximum performance (press release here).

ByAdele Hars
, , , , ,

GlobalFoundries, Verisilicon putting 1st complete IoT modem on single FD-SOI chip

Leveraging GF’s 22FDX® FD-SOI technology, GlobalFoundries and Verisilicon are developing IP to enable a complete cellular modem module on a single chip, including integrated baseband, power management, RF radio and front-end module combining both Narrowband IoT (NB-IoT) and LTE-M capabilities. (Read the full press release here.) The new approach is expected to deliver significant improvements in power, area, and cost compared to current offerings.

The companies say this will be the industry’s first single-chip IoT solution for next-generation Low Power Wide Area (LPWA) networks.  LPWA technology takes advantage of the existing LTE spectrum and mobile infrastructure, but focuses on delivering ultra-low power, extended range, and much lower data rates for devices that transmit small amounts of infrequent data, such as connected water and gas meters.

The two leading LPWA connectivity standards are LTE-M, which is expected to get traction in the U.S. market, and NB-IoT, which is gaining ground in Europe and Asia.  For example, the Chinese government has targeted NB-IoT for nationwide deployment over the coming year. The combination of these two technologies is expected to push cellular M2M module shipments to nearly half a billion by 2021, according to ABI Research.

“Integrated with RF and PA on GF 22FDX, the baseband and protocol stack are being implemented on our energy efficient and programmable ZSPnano that is optimized for control and data flow with powerful low latency, single cycle instructions for signal processing,” said Wayne Dai, VeriSilicon Chairman, President and CEO. “GF’s new 300 mm fab for FDX in Chengdu and IP platforms such as this single chip solution for integrated NB-IoT and LTE-M, will have significant impact on China IoT and AIoT (AI of Things) industries.”

GF and VeriSilicon expect to tape out a test chip based on the integrated solution, with silicon validation in Q4 2017. The companies plan to pursue carrier certification in mid-2018.

 

 

ByAdele Hars
, , , , , , , , , ,

We’re Doing It! FD-SOI Ecosystem Shines in Tokyo (Day 1)

The FD-SOI ecosystem is strong. This was made clear at the recent Tokyo SOI Workshop, organized by the SOI Consortium. The event was spread out over two days, and most of the presentations are now posted (click here to access them).   To cover the full scope of the workshop will take (at least) a couple ASN posts. So let’s start with Day 1, which was billed as the “FD-SOI Ecosystem” day.

A full house for the 3rd Annual Tokyo SOI Workshop, Day 1, FD-SOI Ecosystem(Courtesy: SOI Consortium)

It kicked off with a full-house for an afternoon session in the Yokohama Landmark Tower hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem.

Silvaco:  FD-SOI EDA Pioneer

David Sutton, CEO of EDA provider Silvaco opened the session with his talk, TCAD, EDA & IP to Support FD-SOI. Silvaco has deep FD-SOI roots, having supported Lapis Semi (formerly Oki) in its first forays into the technology – and that was back in 2002! The company is on a growth run this year, having acquired four companies, including IPextreme.

FD-SOI, he said, has been shown to be cost-effective. The capacity is in place, and it’s getting design wins. Silvaco’s full suite of EDA and custom CAD tools for FD-SOI cover the complete design flow from TCAD to sign-off. Their IP is very strong, he said, especially in automotive (including CAN IP), and their partnerships with key players like IBM and NXP are long running. In fact, Silvaco commercializes IP from NXP and others.

GF: FD-SOI Primetime

We got some great insights from Gregg Bartlett, GlobalFoundries’ SVP of the CMOS Business Unit, in his presentation FDX (FDSOI) Goes Mainstream –  Roadmap for Product Competitiveness (it’s posted – click here to download it). “It is primetime for FD-SOI,” he said, and since one technology does not fit all, they’re redefining the mainstream.  GF’s first FD-SOI offering, 22FDX, was qualified in March, and 12FDX will be taping out in the second half of 2018. They’ve currently got over 80 active engagements.

(Courtesy: GlobalFoundries, SOI Consortium)

FD-SOI will be strong in China, he said. GF and the Chengdu municipality recently announced they are investing more than $100 million to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. This will lower the barriers to entry and increase IP availability even further, he said. They’re looking to put 500 design engineers in place. Customer tape-outs of 22FDX will begin at the new fab there in 2H2018, with volume production expected to start in 2019.

He went on to drill down on FDX applications, focusing on four main areas:

  • mobility: application processors that need high performance, RF integration and significant power reduction

  • IoT: this was the target when FDX was first conceived, and it continues to be a point of significant investment by the company

  • RF and mmWave: for BLE (Bluetooth Low Energy), WiFi, ZigBee and integrated PA’s (aka power amplifiers – where they’re seeing some impressive numbers, he said)

  • automotive: Grade 2 is done, and Grade 1 is underway (these are industry ratings related to reliability at the high-temperatures you get under the hood and in hotspots in the passenger compartment).

Citing a slide of customer testimonials, he concluded that the ecosystem is really starting to work, adding that they’ve got the right technology for the right applications, and it’s the right path for them to be on.

Invecas IP & Services

Invecas has been working on 22FDX since 2015 through a strategic partnership with GF. They’ve optimized IP and offer ASIC services, explained Bhaskar Kolla, the company’s Sr. Director of BizDev & Customer Engineering. His presentation, Invecas IP Portfolio in 22FDX is posted – click here to get it. It’s full of detail (standard cells, memories, analog & IO, and interface), so you’ll really want to check it out. The IPs are silicon proven and validated; the results are available, he said.

The foundation IPs are sponsored by GF, so they’re free to customers and cover a broad array of calibrations. They include forward and reverse body biasing (FBB and RBB) and body bias generator IP. Customers are really taking advantage of this, he said, citing as an example one that’s going for 2.5GHz by leveraging FBB.

Custom IP for analog & IO is a place they’re seeing a lot of interest, he continued, and on which they’re doing more and more work with clients. And their Interface IP is in a lot of silicon, especially for customers that are area sensitive. In fact, they’ve developed their own Interface IP demo platform in-house, from build through test and compliance checks.

In moving to FD-SOI, customers are seeing significant PPA improvements, he said. In one of the customer use cases for a high-level IoT product he cited, the customer requirements were easily achieved: cutting leakage in half, dynamic power consumption by roughly a third and area by 20%.

Leti: boosting at 10nm

There’s so much technical detail on performance boosters in Laurent Grenouillet’s presentation, FD-SOI: a Low Power, High Performance Technology Scalable Down to 10nm, you really just have to look at it yourself – click here to get it. A CMOS & Memory Integration Expert at Leti, he did a quick review of 28-22-14nm, then took a deep dive into the myriad of performance boosting options for 10nm, including impressive benchmarking regarding the effectiveness of mobility boosters on FD-SOI vs. FinFET.

Here are the boosters he detailed for 28-22-14nm:

(Courtesy: CEA-Leti, SOI Consortium)

Interestingly he noted that with each node, the thickness of the insulating BOX layer of the SOI wafer scales down, and as it does, back bias efficiency improves even more.

Here’s what he then covered for 10nm (and detailed with data packed in the 20 slides that followed):

(Courtesy: CEA-Leti, SOI Consortium)

FD-SOI is the sweet spot when you need lower power, lower cost, more sensing (analog), more comm (RF), more flexibility and more energy efficiency, he concluded – and he provided powerful data to back that up.

Attopsemi’s non-breaking fuse

I-fuseTM: the best OTP of Choice for FD-SOI and sub-14nm nodes was the topic of a talk by Attopsemi Technology’s Chairman, Shine Chung (you can get the ppt here). The company recently joined GF’s FDXcelerator partner program. OTP stands for one-time programmable memory, and I-fuse is different from other OTP technologies (notably NVM and e-fuses), he explained, in that it’s a non-breaking fuse with ultra-high reliability even in high-temp conditions. It’s been qualified by companies worldwide and is in volume production.

He’s a big fan of FD-SOI because it offers the best RF integration, small form factor, ULP and low cost. Want to make a cellphone as small as a watch? Then you need FD-SOI, he quipped with a tip of the hat to a Dick Tracy image. The fact that FD-SOI has a lower junction breakdown than bulk makes I-fuse the best choice for it, he said. You just program a gate as a fuse.

Get it out the door, fast!

During breaks (on both days!), everybody was talking about the terrific Product Design Methodology presentation by Christophe Tretz, the SOI Consortium’s design guru (and longtime IBM guy). In fact, Christophe has agreed to write it up for ASN in the weeks to come, so don’t miss that. You’ll want to look at the whole presentation — click here to get it.  In the meantime, here are some highlights.

(Courtesy: SOI Consortium)

He suggests designers consider an incremental approach in which FD-SOI benefits accrue. “No, you don’t have to know everything about the technology to use it,” he began (especially addressing those in smaller design teams and houses). “The ecosystem is there. Everything you need to use it is there.”

He used a number of cases to explain.

  • Case 1: a simple, digital SOC – you get significant power savings just by reusing existing library blocks and doing minor recompile.

  • Case 2: RF/mixed-signal – turnaround time is very fast (Analog Bits, for example cut leakage by 5x in a port that took just three months). FD-SOI gives analog designers a great new thing to play with for big power savings – and they learn fast.

  • Case 3 (= Cases 1 + 2): “complex” SOC with RF blocks – rework the RF blocks, but reuse library elements for the digital part without a lot of design effort. You get significant power savings very easily.

  • Case 4: a more complex SOC – in this case, you optimize or customize a few blocks in the first design pass, but then optimize/customize more blocks in subsequent design passes. It just keeps getting better and better.

  • Case X: a fully optimized SOC. This takes more time, but you can do parts in parallel and get dramatic results – especially if you use body biasing.

He then looked at the state of the ecosystem:

  • three fabs are ready

  • we have the tools (Synopsys, Cadence, Silvaco)

  • the libraries are there and ready to use

“You don’t have to learn everything to get your product out the door,” he concluded. “You don’t have to do it all at once: you can do it incrementally. Within a few months, you’ll have a nice product, and as you do new products every six months, each time you can re-use, but also tune for more improvements.”

In short: just do it!

So that’s a recap of Day 1. Next post (or posts?) I’ll recap Day 2. Stay tuned!

ByAdele Hars
, , , , , , ,

$100M+ investment for FDX™ FD-SOI Chengdu design center of excellence

(Source: Google Maps)

GlobalFoundries  and the Chengdu municipality plan to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. They’ve announced an investment of more than $100 million, which is expected to attract leading semiconductor companies to Chengdu, making it a center of excellence for designing next-generation chips in mobile, IoT, automotive and other high-growth markets.

This follows hard on the heels of the partners’ announcement that they’re building a 300mm fab in Chengdu to meet accelerating global demand for GF’s 22FDX® FD-SOI technology.

The partners’  plan is to establish multiple centers focused on IP development, IC design and incubating fabless companies in Chengdu, with the expectation of hiring more than 500 engineers to support semiconductor and systems companies in developing products using 22FDX for mobile, connectivity, 5G, IoT, and automotive. There will also be a focus on creating partnerships with universities across China to develop relevant FD-SOI coursework, research programs and design contests.

Support for the plan is pouring out from across the ecosystem (read the press release here for all the quotes).

“This new design and IP ecosystem in Chengdu is exactly what the Chinese fabless industry needs to take advantage of the game-changing features of FD-SOI, ” says Dan Hutcheson, CEO and Chairman of VLSI Research.  “The initiative is well positioned for success, considering GF’s track record of positive private-public partnerships to grow ecosystems around its fabs in Germany and New York.”

 

 

 

ByAdele Hars
, , , , , , , , , , , , , ,

Body Biasing: It’s Not an Obligation, It’s an Opportunity. And Other Take-Aways from the FD-SOI Design Tutorial Day.

Over a hundred chip designers packed the room for the SOI Consortium’s recent FD-SOI Design Techniques Tutorial Day. Five professors and scientists from top institutions covered design techniques with real examples in digital, mixed-signal, analog, RF, mmW and ULV memory.

Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”

Many of the questions pertained to body biasing, which prompted STMicroelectronics Fellow and Professor Andreia Cathelin to state what may well have been the take-away of the day. “Body biasing is not an obligation,” she said. “It’s an opportunity.”

Q& A with the professors at the end of the FD-SOI Tutorial day. (Courtesy: SOI Consortium)

The tutorial, sponsored by both Samsung and GlobalFoundries, was hosted by Samsung at their San Jose headquarters.  But as this was a paying event, the presentations are only available to those who attended.  Having had the good fortune to attend, I can give you a quick recap of some of the highlights.

Analog, Mixed-Signal and mmW Design: The Overview

Professor Cathelin set the stage with a basic overview of FD-SOI design for analog, mixed-signal and mmW.

FD-SOI is a perfect match for the many up and coming SOCs that are often half analog and/or RF and mmW.  She explained how FD-SOI makes the analog designer’s life much easier (no small feat, since analog can seem rather like blackbox magic to those on the digital side).  FD-SOI improves: performance (even at high frequencies), noise, short device efficiency and brings in a new very efficient transistor knob through the Vt (threshold voltage) tuning range. She also explained and gave numerous real examples implemented in ST’s 28FDSOI on how:

  • forward body bias (FBB) can be used as a Vt tuning knob, giving the designer a very large Vt tuning range, both for analog/RF and mmW designs;
  • the improved analog performance gives you lower power consumption;
  • transistors can operate with decent design margins at L>Lmin.

For mmW design, the transistor should operate at Lmin, and hence you get excellence performance in terms of both transition frequency (Ft – set by the technology node) and maximum frequency (Fmax – what the designer can really get in the gain vs. speed trade-off). This can be conjugated with the fact that the back-end of line, despite the very fine nm node, takes advantage of the SOI features and brings in very decent quality factors.

For mixed-signal/high-speed design, she showed how and why FD-SOI gives you improved variability, a fantastic switch performance, and reduced parasitic capacitance. All these permit state of the art results in high-speed data converters, or, for example, lower frequency implementations which do not need any specific calibration for best in class linearity and ENOB (effective number of bits).

She also presented details on the CEA-Leti electrical models which are now the reference stand point (Leti-UTSOI2) for any FDSOI technology, and are implemented in several industrial Design Kits such those from ST.

RF, mmW and Broadband Fiber-Optic SOCs

Next on tap was a very lively talk with almost 60 slides by Professor Sorin Voinigescu of U. Toronto.  He focused on how to use the main features of FD-SOI for efficient design of RF, mm-wave and broadband fiber-optic SOCs.  We’re talking high-speed/high-frequency here, and he had real examples of chips fabbed in ST’s 28FDSOI and some simulated in GlobalFoundries’ 22FDX technology.

Last slide from Professor Voinigescu FD-SOI tutorial. (Courtesy: U.Toronto, SOI Consortium)

He examined layout issues and gave measurement tips and tricks, noting that there are a lot of things you can do in FD-SOI that you can’t do in bulk.  It’s also easier to get high linearity in FD-SOI – yet another reason that he really likes it.  Plus he sees it as competitive in terms of scaling even past 7nm.

ULV Memories

Professor Joachim Rodrigues of Lund University in Sweden (the largest university in Scandinavia) talked about Design Strategies for ULV memories in 28nm FD-SOI (ST’s FD-SOI technology). Noting that SRAMs eat a lot of area in an SOC, he first proposed a standard cell-based memory (SCM) in 28nm FD-SOI that cut memory area by 35% and reduced leakage by 70%.

Professor Joachim Rodrigues of Lund University presenting at the 2017 FD-SOI Design Techniques Tutorial Day in Silicon Valley (Courtesy: Lund U., SOI Consortium)

He then talked about other chips he and his team have presented at the world’s top chip conferences, including an ultra-low voltage (ULV) SRAM.  For that chip they lay claim to having the best write performance in ULV in sub-65nm (15MHz at 240mV), and the  best performing read capability across all technologies (30MHz at 240mV). In each case, he explained the fundamental design considerations, concepts and trade-offs.

Berkeley: 10 FD-SOI Chips – and Still Counting!

Professor Borivoje “Bora” Nikolic of UC Berkeley is an expert in body-biasing for digital logic. He and his team have designed ten chips in ST’s 28nm FD-SOI, and they’re now working on their 8th generation of energy-efficient SOCs. During his 90-slide (!) tutorial, Energy-Efficient Processors in 28nm FDSOI, he covered: digital logic (including implementation and adaptive tuning of cores for optimal energy efficiency); SRAM and caches (design scenarios and results compared to bulk); supply (generating, switching and analog assists); back bias (how it’s generated and how to use it). He finished with (60 slides of!) design examples and the results they got for power (including adaptive voltage scaling) and performance. He said to be on the lookout for upcoming publications on (even more!) chips, as well as new work on 22nm designs.

A page from Professor Nikolic’s tutorial on FD-SOI design for digital logic. (Courtesy: UC Berkeley, SOI Consortium)

Pushing the Mixed-signal Envelope

Even if you don’t know anything about mixed-signal design, you can walk away from an hour-long lecture by Professor Boris Murmann of Stanford with a good understanding of what it’s all about. In his talk, Pushing the Envelope in Mixed-Signal Design Using FD-SOI, he explained how a mixed-signal person thinks about FD-SOI, and how the different metrics and sweetspots vary depending on what you’re working on.  From there it was the deep dive, as he got into the heart of his talk: simulated transition frequency vs. gm/lD. He explained that while some things might seem counter intuitive (like long channels are more efficient for very low Ft requirements), it’s all related to electrostatics. It’s not yet well explained in the literature, he said, but it should be a big deal.  And he explained why with FD-SOI, you don’t have to design for the worst case. He then talked about where he sees things going – he sees a very bright future indeed for FD-SOI and analog as computing moves into very low-power neural networks. In the end, he said, it all boils down to the FD-SOI performance benefits with respect to better gate control. This translates into “significant improvements” for many mixed-signal/RF building blocks.

Professor Boris Murmann talks about FD-SOI for mixed-signal. (Courtesy: Stanford, SOI Consortium)

All in all, it was a really terrific day. BTW, this tutorial day followed a full-day FD-SOI Symposium in Silicon Valley. Click here to read about that.

ByAdele Hars
, , , , , , , , , , , , , , ,

Upcoming SOI/FD-SOI Workshop in Tokyo – Great Line-Up, Registration Still Open

Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.

This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.)  You’ll find the full program here. A brief summary follows.

(©Tokyo Convention & Visitors Bureau)

Day 1

The first day – Wednesday, May 31st  – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.  

It will take place on the 25th floor of the Yokohama Landmark Tower.  The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.

Day 2

The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.  

It kicks off with talks on ultra-low power applications from Sony IoT and Samsung.  Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure.  The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.

Coffee breaks and lunch will give attendees and speakers time for further discussion.

This is a great opportunity – don’t miss it!

Search

Recent ASN Posts

Advanced Substrate News Sign Up

Follow us on Twitter

© SOI Industry Consortium 2019