Tag Archive high-perf

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here).

In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you do with your phone – snapping pictures, listening to music, watching video, oh yeah, even talking and listening –  involve the DSP’s number-crunching prowess. It takes real-world analog information that describes sound, pressure, light, and temperature and mathematically optimizes and processes them in real-time, so the data can be displayed, analyzed, compressed, enhanced, or converted. The DSP’s raison d’etre is to maximize work-per-clock-cycle.

When product designers talk about “user engagement” with their portable device, chances are there’s a DSP involved. And the better the DSP does its job, the cleaner your sound, the clearer your picture, the faster your download, and the more easily you can converse. But all this processing comes at a price – an energy price.  Chip designers are always looking for better ways to improve the power-performance trade-off, so that we as users get all this great performance without running out of batteries.

Power is directly proportional to clock frequency (MHz, GHz) and the square of the voltage that’s supplying the device. So, if you have a device that operates at higher frequencies with lower supply voltages, you’ve got a big edge on saving power – and of course, the less power you pull from your battery, the longer your battery will keep you snapping, listening, watching, and conversing.

That’s what’s at play here with this Leti/ST news. They’ve demonstrated a DSP that can hit 500 MHz while pulling just 460mV – that’s ten times better than anything the industry’s seen so far.

In fact, Fabien Clermidy, head of Digital Design and Architecture at Leti told ASN that this could mean extending your battery life by about another 30% for typical usages.

Leti and ST showed the FD-SOI DSP at ISSCC – the IEEE’s International Solid-State Circuits Conference (February 2014), which is widely considered the premier forum for presenting advances in solid-state circuits and SOCs.

 

Ultra-Wide Voltage Range

Specifically, at ISSCC Leti and ST presented the successful demonstration of an ultra-wide-voltage range (UWVR) DSP, based on 28nm ultra-thin body buried-oxide (UTBB = ST and Leti’s flavor of) FD-SOI technology.

This may be the first you’ve heard of Leti/ST’s UWVR, but it’s been making the conference rounds over the last year. Leti/ST presented it at the DATE Conference in 2013. (You can get the paper on the IEEEXplore site – click here.) In that paper, Leti and ST engineers demonstrated the technology on an ARM A9, where they showed performance boosted by 40% to 200% without added energy cost. Conversely, when saving power is more important than boosting performance (which turns out to be about 90% of the time!), FD-SOI reduced leakage power by a factor of 10 using Reverse Body Biasing.

Leti and ST also presented FD-SOI in the memories section at ESSCIRC ’13, where they applied it to a 28nm FD-SOI SRAM bitcell array, noting “…over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.” (This paper is also available from the IEEEXplore site – click here.)

In the case of the demonstrator DSP presented at ISSCC, the demonstrator was  produced by ST in their 28nm UTBB FD-SOI process technology. The UTBB FD-SOI allows:

  • body-bias-voltage scaling from 0V to +2V,
  • decreased minimum circuit operating voltage,
  • and clock-frequency operation of 460MHz at 400mV.

To the UWVR innovation, ST and Leti have added optimized standard-cell libraries they had developed to cover the 0.275V to 1.3V range. They then were able to leverage the voltage scaling they get with FD-SOI with system clocking techniques in the optimized cells, including:

  • non-overlapping pulses;
  • fast pulse-triggered flip-flop devices designed for variability tolerance at low voltage;
  • monitoring on-chip timing-margins to dynamically adjust the clock frequency to a few percent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.

As a result, even at 0.4V, the DSP exhibits 10x better operating frequency than the previous state-of-the-art.

ISSCC14_ST_Leti_FDSOI_DSP

(Courtesy: ISSCC, STMicroelectronics, CEA-Leti)

Clermidy also adds that their innovative design techniques reduced design margins, thus avoiding over-design. Again, doing this in FD-SOI rather than bulk was key, since FD-SOI really reduced variability issues.

The Leti/ST ISSCC paper, which is entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented on Feb. 12, during Session 27, “Energy-Efficient Digital Circuits..  A demonstration kit was shown to attendees. As of this writing, it’s not yet been posted on the IEEEXplore site, but it should be in the weeks to come.

New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP

D+R_ST_FDSOIslideDesign & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.

After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm).  He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.

AMD’s second generation A-Series Accelerated Processing Units is now available in retail and distribution channels

Based again on 32nm SOI, AMD‘s second generation A-Series Accelerated Processing Units (APUs) (formerly codenamed “Trinity”) for mainstream and ultrathin notebooks, All-in-One and traditional desktops, home theater PCs and embedded designs is now available in retail and distribution channels. The new x86 cores, codenamed “Piledriver,” are an evolution of the revolutionary “Bulldozer” cores with some major performance enhancements, hitting up to 4.2 GHz. But consumer-savvy reviewers also cite the impact of Trinity’s excellent performance-per-watt on battery life.

EXCLUSIVE ASN INTERVIEW: ST’s Jean-Marc Chery on FD-SOI Manufacturing

In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it particularly well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

STMicroelectronics fab in Crolles, France

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

ST Crolles fab

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.

Roundup: FD-SOI & Ecosystem Shine at Semicon West

A major highlight at this year’s Semicon West in San Francisco was a panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry.  It was an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

  • ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
  • GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
  • IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
  • SOI Industry Consortium: Horacio Mendez – Executive Director
  • Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
  • STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
  • UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI & Ecosystem Shine at Semicon West

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs, where in the past it was CPUs and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out out products, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm next month.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FDSOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show, full of energy and renewed enthusiasm.

GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers

Two big pieces of news have just been announced by STMicroelectronics:

  1. to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices;
  2. ST will open access to its FD-SOI technology to GlobalFoundries’ other customers.

The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Here are other key points from the press release:

  • The 28nm FD-SOI generation, currently in the industrialization phase, is scheduled to be available for prototyping by July 2012.
  • The next node, the 20nm FD-SOI generation, is currently under development and is scheduled to be ready for prototyping by Q3 2013.

What they’re saying:

Joel Hartmann, STMicroelectronics Corporate VP, Front End Manufacturing and Process R&D, Digital Sector: “FD-SOI is ideally suited for wireless and tablet applications, where it provides fully-depleted transistor benefits using conventional planar technology, and this arrangement with GLOBALFOUNDRIES ensures our customers will have a secure source of supply.”

Philippe Magarshack, STMicroelectronics Corporate VP, Design Enablement and Services: “Porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to Bulk, due to the absence of MOS-history-effect. In addition, FD-SOI can be used for either extreme performance or very low leakage on the same silicon, by biasing dynamically the substrate of the circuit. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.”

Gregg Bartlett, Chief Technology Officer of GLOBALFOUNDRIES: “We have a longstanding partnership with ST spanning joint R&D and manufacturing, as well as an unmatched heritage of expertise in SOI technology. We’re pleased to be working with ST to bring this next generation of SOI technology to market and enable continued momentum in the mobile revolution.”

While it might seem like all this is happening very fast, ST has been championing FD-SOI technology for about a decade. In fact, one of the company’s top SOI gurus, Advanced Devices Program Director Thomas Skotnicki, first wrote about it for us here at Advanced Substrate News back in 2006. And we’ve been covering it regularly ever since.

For an in-depth look at ST’s FD-SOI design and manufacturing strategy and benchmarking results, be sure to check out their white paper. By the way, designers take note: they also indicate in the white paper that the 28nm FD-SOI Process Design Kit (PDK) is available now, targeting risk production by mid-2012. Evaluation SPICE models are now available for the 20nm node, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

For easy access to the dozens of useful and insightful FD-SOI related articles by contributors on the leading-edge that we’ve published over the years, just hit the FD-SOI tag on the ASN website.

Seems like a new door has opened now, doesn’t it?

Global Foundries Fab8

Fab 8, located in Luther Forest Technology Campus, Saratoga County, New York, USA is GlobalFoundries’ new 300 mm Fab dedicated to advanced technologies. Maximum Full Capacity is 60,000 300mm wafers/month. GloFo also runs high-volume SOI at its fabs in Dresden and Singapore (source: Wikipedia).

NovaThor SmartPhone Chip on 28nm FD-SOI: ST-Ericsson Blogger Tells All; PC Mag Sees Light

To paraphrase the song, “What a difference a day would make.”  Searching to plug into the nearest power strip each afternoon, active smartphone users would certainly agree with that. But ST-Ericsson’s next-gen NovaThor chips on 28nm FD-SOI (available for design now), which are looking to get an extra day out of your battery, should put an end to that refrain.

In a recent article, PC Magazine’s Sascha Segan reports on a next-gen NovaThor (two 1.85GHz ARM Cortex-A9 processors). As he notes, “It’s speedy, but its real pitch is low power and low cost.” Marc Cetto, ST-Ericsson’s senior vice president for smartphone and tablet solutions explained to him that when moving to fully depleted silicon-on-insulator technology (FD-SOI), the two cores will run at extremely low power, especially when only low clock speeds are needed, which is actually most of the time.

Noting that the core strategy resembles nVidia’s “companion core” approach, Cetto explained to Segan that FD-SOI will let ST-Ericsson, “… run its main core at 400MHz like a ‘companion’ core without the extra cost and space of a whole extra core.” Furthermore FD-SOI will run more clock cycles at lower power, he continued, “…enabling ST’s chips to chug along at 1GHz at 0.6 volts while competitors need 0.9 volts for 1GHz.” That will amount to a 30 percent power savings, with even lower voltages possible at lower speeds.

How do they do it?  ST-Ericsson’s principle engineer on the project, Valery Gravoulet, recently wrote an excellent series of tech blogs entitled FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor. His explanations and terrific graphs show why FD-SOI is blowing the bulk competition away.

Here’s a graph from his first blog, comparing the three 28nm technologies – high performance bulk (HP), low power bulk (LP), and FD-SOI –  in terms of high performance (GHz) vs. supply voltage (VDD):

STE performance comparison of 28nm-technologies

Gravoulet concludes, “So, over a large Vdd range (from 0.5V up to 1.3V), FD-SOI comprehensively outperforms existing bulk CMOS processes dedicated to mobile applications. This extra performance gain can be used either to increase peak performance or to operate at a lower Vdd for the same performance, saving dynamic power.” (For a complete explanation, click here to read  part 1 of his blog.)

We’re now all coming to appreciate that our phones’ power usage comes in two flavors: the “dynamic” power needed to run the chip, and the “leakage” that’s just lost over time.  In the second part of the Gravoulet/ST-Ericsson blog series (which you can read and see the graphs by clicking here), he first looks at the speed/leakage trade-off.  He concludes:  …for the same leakage budget, FD-SOI at nominal voltage (1.0V) is systematically faster than either the LP process at nominal voltage (1.0V) or the HP process at nominal voltage (0.9V).

He then turns to power efficiency.  As his graph shows, “for a given frequency , the total dynamic power consumption is always considerably lower – even if FD-SOI requires a slightly higher supply voltage than 28 “HP” to reach the target frequency. […] This behavior can be seen across the whole voltage and corresponding performance range demonstrating clearly that FD-SOI is the solution that gives the best power efficiency for mobile devices.”

Happily, we should be reaping the benefits of this move to 28nm FD-SOI in smartphones from ST-Ericsson customers (and they are fast building up an impressive list for the NovaThor line) early next year.  And volume won’t be a problem, since they have both ST and a foundry lined up. (See slide #21 from the JM Chery’s presentation at the STMicroelectronics NV 2012 Investors & Analysts Day in NY a few weeks ago.)

Til then, anyone see a free outlet I can plug my charger into?

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Work at Leti shows that strain is an effective booster for high-performance at future nodes.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Stressor options for FD-SOI technology

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Efficiency of stressor techniques for N & PMOS

Figure 2: Efficiency of stressor techniques for N & PMOS

 

In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.

– – – – –

References:

[1] C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu,

T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

[2] S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator

(sSOI)”, Solid State Electronics, 2010.

[3] F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI

and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.

[4] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-

On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.

[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,

A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with

HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.

From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec):

“ FD-SOI Executive Summary

Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too.

At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors.

Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer.

Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments. ”

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

ST Technology Overview

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section):

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    – further improved electrostatic control and relaxed thinness requirement of the top silicon,

    – enables back-biasing through the BOX,

    – enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    – brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that

the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)


Excellent
speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)


Focus on SRAM: 
The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline


SPICE
Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

Perspectives

28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length.

The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.

The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface  when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.

The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.

Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:

  • Higher speed and lower leakage
  • Lower supply voltage (Vdd) and power consumption
  • Further scaling and lower cost
  • Better sub-threshold swing and scaling
  • No random dopant fluctuation (RDF), less variability
  • Better mobility, especially for future sub-threshold design

FinFET

The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.

FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.

While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of  bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.

Berkeley

When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.

Planar FD-SOI

Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon.  When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.

However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.

The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.

While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.

Conclusion

This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.