Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here).
In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you do with your phone – snapping pictures, listening to music, watching video, oh yeah, even talking and listening – involve the DSP’s number-crunching prowess. It takes real-world analog information that describes sound, pressure, light, and temperature and mathematically optimizes and processes them in real-time, so the data can be displayed, analyzed, compressed, enhanced, or converted. The DSP’s raison d’etre is to maximize work-per-clock-cycle.
When product designers talk about “user engagement” with their portable device, chances are there’s a DSP involved. And the better the DSP does its job, the cleaner your sound, the clearer your picture, the faster your download, and the more easily you can converse. But all this processing comes at a price – an energy price. Chip designers are always looking for better ways to improve the power-performance trade-off, so that we as users get all this great performance without running out of batteries.
Power is directly proportional to clock frequency (MHz, GHz) and the square of the voltage that’s supplying the device. So, if you have a device that operates at higher frequencies with lower supply voltages, you’ve got a big edge on saving power – and of course, the less power you pull from your battery, the longer your battery will keep you snapping, listening, watching, and conversing.
That’s what’s at play here with this Leti/ST news. They’ve demonstrated a DSP that can hit 500 MHz while pulling just 460mV – that’s ten times better than anything the industry’s seen so far.
In fact, Fabien Clermidy, head of Digital Design and Architecture at Leti told ASN that this could mean extending your battery life by about another 30% for typical usages.
Leti and ST showed the FD-SOI DSP at ISSCC – the IEEE’s International Solid-State Circuits Conference (February 2014), which is widely considered the premier forum for presenting advances in solid-state circuits and SOCs.
Ultra-Wide Voltage Range
Specifically, at ISSCC Leti and ST presented the successful demonstration of an ultra-wide-voltage range (UWVR) DSP, based on 28nm ultra-thin body buried-oxide (UTBB = ST and Leti’s flavor of) FD-SOI technology.
This may be the first you’ve heard of Leti/ST’s UWVR, but it’s been making the conference rounds over the last year. Leti/ST presented it at the DATE Conference in 2013. (You can get the paper on the IEEEXplore site – click here.) In that paper, Leti and ST engineers demonstrated the technology on an ARM A9, where they showed performance boosted by 40% to 200% without added energy cost. Conversely, when saving power is more important than boosting performance (which turns out to be about 90% of the time!), FD-SOI reduced leakage power by a factor of 10 using Reverse Body Biasing.
Leti and ST also presented FD-SOI in the memories section at ESSCIRC ’13, where they applied it to a 28nm FD-SOI SRAM bitcell array, noting “…over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.” (This paper is also available from the IEEEXplore site – click here.)
In the case of the demonstrator DSP presented at ISSCC, the demonstrator was produced by ST in their 28nm UTBB FD-SOI process technology. The UTBB FD-SOI allows:
To the UWVR innovation, ST and Leti have added optimized standard-cell libraries they had developed to cover the 0.275V to 1.3V range. They then were able to leverage the voltage scaling they get with FD-SOI with system clocking techniques in the optimized cells, including:
As a result, even at 0.4V, the DSP exhibits 10x better operating frequency than the previous state-of-the-art.
(Courtesy: ISSCC, STMicroelectronics, CEA-Leti)
Clermidy also adds that their innovative design techniques reduced design margins, thus avoiding over-design. Again, doing this in FD-SOI rather than bulk was key, since FD-SOI really reduced variability issues.
The Leti/ST ISSCC paper, which is entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented on Feb. 12, during Session 27, “Energy-Efficient Digital Circuits.. A demonstration kit was shown to attendees. As of this writing, it’s not yet been posted on the IEEEXplore site, but it should be in the weeks to come.
Work at Leti shows that strain is an effective booster for high-performance at future nodes.
The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.
As illustrated in Figure 1, strain can be incorporated at various places in the transistor:
First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si.
We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.
For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors . Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL for NMOS and with rotated substrates, e-SiGe, SiGe channels and (110) substrates for pMOS.
For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel). Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).
In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.
NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.
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FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length.
The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd), resulting in excessive power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.
The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.
The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.
Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:
The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.
FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.
While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.
When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.
Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon. When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.
However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.
The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.
While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.
This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.