Tag Archive IBM

Shanghai More-Than-Moore Presentations Now Posted on SOI Consortium Website

Presentations given at the ‘Beyond Computing’ Innovative Technologies Symposium (March 2015 in Shanghai) are now available on the SOI Consortium website (click here to see the list). The Symposium covered MEMS, semiconductor manufacturing, RF and power, which are key topics for the fast growing “More than Moore” industry. The one-day, closed-door symposium was organized by members of the SOI Consortium and the Shanghai Industrial μTechnology Research Institute (SITRI) to facilitate exchanges with industry leaders in China.

RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more)

RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.

In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.

The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.

IBM

IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.

IBM_RFSOI_LTE

 

Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.

IBM_RFSOI_IoT

He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.

IBM_RFSOI_wafers_lowres

(You might also want to also refer to the IBM RF-SOI presentations given recently in Shanghai and Tokyo.)

ST

In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.

ST_RFSOI_roadmap

Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.

ST_RFSOI_PA

ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)

GlobalFoundries

In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.

GF_RFSOI_why

GF is the foundry partner for Peregrine (now part of Murata), and he showed how the GlobalONE PA integration is an excellent example of innovation opportunities.

GF_RFSOI_Peregrine

With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.

GF_RFSOI_FDSOI_filters

 

Incize

Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.

Imec

Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.

More Workshops Coming

If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

Top Silicon Valley Companies Signed Up for FD-SOI & RF-SOI Forum (27 Feb. 2015 in SF, free, registration still open)

Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.

FDSOI_SF15_workshopIf you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.

Morning session: FD-SOI Workshop

FD-SOI foundry offer

  • FD-SOI Advantages for Applications and Ecosystem — Philippe Magarshack, CTO, STMicroelectronics
  • 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm — Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI
  • [Title TBA] — Jamie Schaeffer, GlobalFoundries

FD-SOI IP offer

  • Synopsys FD-SOI IP Solutions — Mike McAweeney, Sr. Director IP Product Sales, Synopsys
  • FD-SOI: Ecosystem and IP Design — Amir Bar-Niv, Senior Group Director, Product Management, Design IP, Cadence

FD-SOI design experience

  • [Title TBA] — N. Ben-Hamida, High speed Analog Design Manager, Ciena
  • 28nm FD-SOI Design/IP Infrastructure — Shirley Jin, Sr. Director of Engineering, Verisilicon

Panel discussion

Advantages and opportunities when designing with FD-SOIModerator: Dan Nenni, SemiWiki

Panelists:

  • Marco Brambilla, Director of Engineering, Synapse
  • Wayne Dai, Chairman, President & CEO, VeriSilicon
  • Kelvin Low, Sr Director, Foundry Marketing, Samsung SSI
  • Philippe Magarshack, CTO, STMicroelectronics
  • Guntram Wolski, Cisco Systems

Innovation

  • Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator — Mike Noonen, Chairman & Co-founder, Silicon Catalyst

Afternoon session: More than Moore Forum

  • RFSOI: Redefining Mobility and More in the Front-End – Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group
  • Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers — Barend Van Liempd, PhD Researcher, IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,)
  • RF SOI: from Material to ICs – an Innovative Characterization Approach — Mostafa Emam, CEO, Incize
  • ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration — Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics

If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.

This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.

For the SF event – here’s the key information:

FD-SOI and RF-SOI Forum

  • Friday, February 27th, 2015, 8am to 6pm
  • Palace Hotel
  • 2 New Montgomery Street, San Francisco, California, 94105 (USA)

The event is free but pre-registration is mandatory – click here to sign up on the SOI Consortium website.

Tokyo FD-SOI/RF-SOI Workshop (part 1): Samsung, ST presentations & more

A dozen excellent presentations on FD-SOI and RF-SOI were made by industry leaders at the recent workshop in Tokyo. Here in part 1 of ASN’s coverage, we’ll take a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis.

In part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

28FD-SOI: cost effective low power solution for long lived 28nm node by Yongjoo Jeon, Principle Engineer in Foundry Marketing, Samsung

This presentation makes the point that cost and power are equally critical
 factors in the long life foreseen for the 28nm node. (Samsung, of course, is offering ST’s FD-SOI technology on a foundry basis.) In particular, this presentation shows how FD-SOI is especially well-suited for low-power
 IoT apps. (btw, Semiwiki just published an excellent analysis of this Samsung presentation – you can read it here.) The process was successfully qualified in September 2014.

SamsungFDSOI_lowVDD

(Courtesy: Samsung)

SamsungFDSOIprocesscost

(Courtesy: Samsung)

 

FD-SOI advantages for applications and ecosystem by Kirk Ouellette, Director Digital Product Group, STMicroelectronics

As FD-SOI both improves power efficiency and brings high flexibility to SoC integration, this presentation points up the target app benefits:

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

  • For Consumer products, it’s optimized SoC integration with mixed signal and RF; Energy efficiency under all thermal conditions; Optimized leakage in idle mode
  • For IoT, it’s low-cost, ultra-low voltage operation, high scalability and efficient RF and analog integration
  • For networking infrastructure, it’s energy-efficient multicores, effective DVFS and excellent memory performance
  • For automotive, it’s handling leakage at high-temps and high reliability (especially SER re: memory).

RF-SOI: Redefining mobility through the Front End Module by Masashi Arimoto, Technical Executive, Mobile Platform, IBM Microelectronics Japan

In 2006, IBM started transforming a 200mm fab into a specialty foundry. RF-SOI and SiGe were key technologies for cell phone and WiFi front end modules (FEM).  Mobile is key for driving the business of IBM: for infrastructure, for Cloud and for Big Data/analytics. Having shipped over 8 billion RF-SOI chips (>1300 tapeouts) to top mobile customers on its 7RF SOI technology, the company recently announced a new process: 7SW SOI, which packs 30% more performance into a 30% smaller space. They’re seeing ever stronger demand, which IoT will only increase. (Interesting to note that IBM also now sees 300mm FD-SOI as an opportunity for the heart and soul of the cell phone: the application processors.)

(Courtesy: IBM)

(Courtesy: IBM)

RF-SOI and FD-SOI Market Opportunities by Handel Jones, CEO, IBS

Industry guru Handel Jones (read his ASN pieces here) gets into the details of what IoT means in terms of chips, and where and when growth will be happening. Don’t miss his detailed slides on die and wafer cost for the various nodes of FD-SOI, bulk and FinFET (see slides 20-26) – FD-SOI comes out the clear winner in terms of cost benefits. He then explores the various RF segments.

 

ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration by Flavio Benetti, DPG Group VP – Networking Products Division GM, STMicroelectronics

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

Starting with a review of RF trends, this presenation shows how evolutions in the LTE wireless standard for this high-growth market are driving RF Front End Modules (FEM) to unprecedented complexity. ST sees RF-SOI integration as the right answer to that complexity (RF-SOI is of course already the leading technology in smartphone RF switches.) Slide 7 (see illustration) shows the explosive growth in the total annual market (TAM) for RF-SOI wafers. ST’s H9SOI_FEM offering pushes FEM integration to new heights, integrating switching, power amps, antenna tuning, energy management, LNA and filtering, all with best-in-class performance. This is an area in which ST is offering high-capacity foundry services, handling billions of units/year. (ST did an excellent ASN article detailing H9SOI_FEM last year – if you missed it, click here to read it now.)

 

Development of X-ray Sensor with SOI Pixel Technology by Masao Okihara, Device Technology Development Division, Manufacturing Headquarters, LAPIS Semiconductor

This presentation gives on update of the ongoing and fascinating work by a major consortium developing a one-chip monolithic X-ray sensor device on FD-SOI (this was also covered in ASN when the project was first getting underway – you can read that piece here. Oki, which is now Lapis, is providing the foundry services).

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

IBM z13, world’s fastest microprocessor – on SOI, of course!

A 22nm SOI chip is at the heart of IBM’s new z13 mainframe, one of the most sophisticated computer systems ever built. (Augusto Menezes/Feature Photo Service for IBM)

A 22nm SOI chip is at the heart of IBM’s new z13 mainframe, one of the most sophisticated computer systems ever built. (Augusto Menezes/Feature Photo Service for IBM)

The recently announced IBM z13, which is billed as the world’s fastest microprocessor, is built on SOI (of course!) (read the press release here).

At the heart of the latest in the IBM z-series of mainframes, the chip is manufactured in 22nm SOI (partially depleted). IBM says it is 2X faster than the most common server processors, has 300 percent more memory, 100 percent more bandwidth and vector processing analytics to speed mobile transactions. As one of the most sophisticated computer systems ever built, the z13 is the first system able to process 2.5 billion transactions a day, enabling transaction analysis in “real time” to help prevent fraud as it is occurring, allowing financial institutions to halt the transaction before the consumer is impacted.

IBM says the z13 lowers the cost of running cloud. For compared environments, it is estimated that a z Systems cloud on a z13 will have a 32 percent lower total cost of ownership over three years than an x86 cloud and a 60 percent lower total cost of ownership over three years than a public cloud.

The z-series has been on SOI since it first launched in 2003.

2015 – Turning the Tables for FD-SOI, RF-SOI and More

If current momentum is any indication, 2015 will be the year the tables turn in favor of FD-SOI designs (with a big shout-out to IoT).  The RF-SOI juggernaut will continue cutting an enormous swath through the mobile market.   Attention to the exciting possibilities of monolithic 3D (M3D) technology (like Leti’s “CoolCube”) will continue to grow, and SOI-based power apps will continue their strong drive into automotive and other markets. More exciting apps in MEMS, NEMS, photonics and sensors will come over the horizon. Players in China will join the upper echelons of SOI-based design and manufacturing. And you’ll read about it all here in ASN.

Riding on the success of the Shanghai RF-SOI and FD-SOI workshops last fall, 2015’s getting off to a great start with free FD-SOI/RF-SOI workshops in Tokyo (23 January, just after ASP-DAC) and San Francisco (27 February just after ISSCC – click here to register).

FDSOI_SF_logo

As of this writing, we just got the news that registrations for the Tokyo workshop had far exceeded expectations. There’s lots of excitement surrounding the prospect of the Sony presentation on their FD-SOI design experience, which we hear will be excellent.  Samsung is slotted for a full half-hour presentation on their FD-SOI offering.  There’ll be press coverage, and here at ASN we’ll be sure to bring you the full wrap-up.

ST and partners Leti, Soitec and IBM have long been leading the FD-SOI charge.  At IEDM ’14 last month, they showed us how the roadmap extends to 10nm. (If you missed that, click here to read about it.) Now we’re looking forward to hearing about those 28nm FD-SOI chips hitting the markets this year.

And with Samsung on board now for ST’s FD-SOI process, things are looking ever more interesting. Earlier this month, Samsung’s Kelvin Low (Senior Director, Foundry Marketing) noted in his blog that, “28FDSOI comes with a complete design ecosystem” (PDK, Library, IP, and DFM – click here to read about it). “Customers who are looking to manufacture faster, cooler, and simpler devices at 28nm should look no further – 28FDSOI is the ideal choice,” he concluded.

Kelvin will also be presenting in the who’s who line-up at the prestigious Electronic Design Process Symposium (aka EDPS, coming up at Monterey Beach, CA in April – click here for more info.) In fact, the lead session of this year’s EDPS is entitled “FinFET vs. FDSOI – Which is the Right One for Your Design?” We look forward to some lively discussions there!

We heard a lot of promising developments at the Semicon Europa Low-Power Conference in the fall (if you missed that ASN coverage, click here to read it).  Although they’ve been quiet in the press, at the conference it was clear that GloFo foundry guys are chomping at the bit.  To recap, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they have customers lined up, he said yes – so we’ll look forward to hearing about them this year.

And finally, this April we’ll be celebrating the 10th anniversary of ASN. It’s hard to believe 10 years have sped by since we published our first edition. Thank you for your continued support.

With best wishes for a safe, happy, healthy and prosperous 2015.

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

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This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

Strong uptick in FD-SOI patent activity, according to KnowMade report

There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure).  The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies).  More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families.  Following a rush of activity about 10 years ago there was a dip, but activity over the last couple of years has once again been very strong.

The report provides a comprehensive overview, essential patent data for fully depleted SOI, plus a searchable database with links.  It identifies more than 30 patent holders of FD-SOI related intellectual property, providing in-depth analysis of key technology segments and key players. “The major proponents of the FD-SOI technology have strong IP arms, but other unexpected players known as not supporting FDSOI [including TSMC and Intel] are also present,” notes the report.

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

iedm_logoBeyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 2 of ASN’s IEDM coverage, we’ll cover future device architectures. In Part 1, we had a rundown of the top SOI-based advanced CMOS papers. In Part 3 we’ll look at MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

16.2: Dual-Channel CMOS Co-Integration with Si Channel NFET and Strained-SiGe Channel PFET in Nanowire Device Architecture Featuring 15nm Gate Length

P. Nguyen et al (Leti, ST, Soitec)

 

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM 14, Paper 16.2)

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM
14, Paper 16.2)

The researchers have fabricated the first hybrid channel omega-gate CMOS nanowire (NW) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FET. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NW (LG=15 nm) with +90% ION current improvement. [110]-oriented NW is shown to be the best candidate to improve drive current under compressive strain. In this work, the strain is measured by using precession electron diffraction with a 1nm spatial resolution. Furthermore, they show that hybrid integration reduces the delay of CMOS ring oscillator (FO=3) by 50% at VDD=0.9V. Finally, they demonstrate the most aggressively scaled hybrid CMOS NWs reported to date with NW width and gate length down to 7nm and 11nm, while maintaining high drive current (687µA/µm for p-FET and 647µA/µm for n-FET) with low leakage current and excellent short-channel-control (DIBL<50mV/V).

 

20.5: Study of the Piezoresistive Properties of NMOS and PMOS Omega-Gate SOI Nanowire Transistors: Scalability Effects and High Stress Level

J. Pelloux-Prayer et al (Leti, Soitec, Tokyo Tech)

The researchers present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). They show that the downscaling of geometrical parameters doesn’t allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.

 

20.3: Direct Observation of Self-heating in III-V Gate-all-around Nanowire MOSFETs

S.H. Shin et al (Purdue U)

Multi-gate devices, such as, FinFET, Gate-all-around transistors (GAA-FET) improve 3D electrostatic control of the channel, but the corresponding increase in self-heating may compromise both performance and reliability. Although the self-heating effect (SHE) of FinFET appears significant, but tolerable, the same may not be true for GAA geometry, especially in quasi-ballistic regime where hot spots and non-classical heat-dissipation pathways may lead to localized damage. The existing reports of the SHE on the SOI, FinFET or GAA-FET have so far relied either on indirect electrical measurements with inherent temporal delays, or on optical infra-red (λ>1.5μm ) imaging that cannot resolve deep submicron features. As a result, it has so far been impossible to resolve the spatio-temporal features of SHE fully. In this paper, the researchers develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the local temperature rise of GAA-FET with different number of nanowires (NW)(ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW.

 

9.6: In-situ Doped and Tensilely Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828µA/µm, Ion/Ioff ~ 1×105, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement

I-H. Wong et al (Taiwan U)

In-situ CVD doping and laser annealing can reach [P] and tensile strain as high as 2×1020 cm-3 and 0.37%. Junctionless Ge gate-all-around nFETs with 9 nm-Wfin and 0.8 nm-EOT achieves the record high Ion of 828 µA/µm. The Ion enhancement of ~40% is achieved under the tensile strain of 0.25%.

 

27.6: Flexible High-performance Nonvolatile Memory by Transferring GAA Silicon Nanowire SONOS onto a Plastic Substrate

J.-M. Choi et al (KAIST, NASA)

Flexible nonvolatile memory is demonstrated with excellent memory properties comparable to the traditional wafer-based rigid type of memory. This  achievement is realized through the transfer of an ultrathin film consisting of single crystalline silicon nanowire (SiNW) gate-all-around (GAA) SONOS memory devices onto a plastic substrate from a host silicon wafer.

13.2: High Ion/Ioff Ge-source Ultrathin Body Strained-SOI Tunnel FETs – Impact of Channel Strain, MOS Interfaces and Back Gate on the Electrical Properties

M. Kim et al (U Tokyo)

The researchers demonstrated Ge/strained-Si hetero-junction TFETs with in-situ B doped Ge. The increase in channel strain and optimization of PMA have successfully realized high performance of steep SSmin below 30 mV/dec and large Ion/Ioff ratio over 3×107.

13.3: Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective

Q. Huang et al (Peking U)

In this paper, a novel TFET design, called Pocket-mSTFET, is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from a circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated Pocket-mSTFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Circuit-level implementation based on Pocket-mSTFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

13.4: A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

J. Zhang et al (EPFL)

The researchers demonstrate a steep subthreshold slope silicon FinFET with Schottky source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA/μm is also achieved with high Ion/Ioff ratio of 107.

 

26.2: Thin-Film Heterojunction Field-Effect Transistors for Ultimate Voltage Scaling and Low-Temperature Large-Area Fabrication of Active-Matrix Backplanes

B. Hekmatshoar et al (IBM)

Heterojunction field-effect thin-film transistors with crystalline Si channels and gate regions comprised of hydrogenated amorphous silicon or organic materials are demonstrated. The HJFET devices are processed at 200ºC and room temperature, respectively; and exhibit operation voltages below 1V, subthreshold slopes of 70-100mV/dec and off currents as low as 25 fA/um.

 

26.7 Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel for 3D IC Applications

Y.-C. Cheng et al (National Tsing Hua U, National Chiao Tung U)

The hybrid fin poly-Si channel junctionless field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of steep SS (64mV/dec), high Ion/Ioff (>107) and small DIBL (3mV/V). The devices are highly promising for future further scaling and 3D stacked ICs applications.

 

35.1: A Physics-based Compact Model for FETs from Diffusive to Ballistic Carrier Transport Regimes

S. Rakhejaet al (MIT, Purdue U)

The virtual source (VS) model provides a simple, physical description of transistors that operate in the quasi-ballistic regime. Through comparisons to measured data, key device parameters can be extracted. The VS model suffers from three limitations: i) it is restricted to short channels, ii) the transition between linear and saturation regions is treated empirically, and iii) the injection velocity cannot be predicted, it must be extracted by fitting the model to measured data. This paper discusses a new model, which uses only a few physical parameters and is fully consistent with the VS model. The new model: i) describes both short and long channel devices, ii) provides a description of the current at any drain voltage without empirical fitting, and iii) predicts the injection velocity (device on-current). The accuracy of the model is demonstrated by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

 

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This is the 2nd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

 

10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

iedm_logoFD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we have a rundown of the top SOI-based advanced CMOS papers. In Part 2, we’ll cover papers on future device architectures. In Part 3 we’ll look at the papers on MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

 

The FD-SOI Papers

9.1: FD-SOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node.

Q. Liu et al (STMicroelectronics, CEA-LETI, IBM, Soitec)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In this work, researchers from STMicroelectronics and the IBM Technology Development Alliance demonstrate the successful implementation of strained FDSOI devices with LG, spacer & BOX dimensions scaled to 10nm feature sizes.

Two additional enabling elements for scaling FD-SOI devices to the 10nm node are reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 µA/µm for NFET at Ioff=1 nA/um (the highest performing FD-SOI NFET ever reported), and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 µA/µm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL are also reported.

 

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14. (Courtesy: ST et al, IEDM 2014)

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14.
(Courtesy: ST et al, IEDM 2014)

7.2: A Mobility Enhancement Strategy for sub-14nm Power-efficient FDSOI Technologies

B. De Salvo et al. (Leti, ST, IMEP, IBM, Soitec)

This paper presents an original multi-level evaluation methodology for stress engineering device design of next-generation power-efficient devices. Ring oscillator simulations showed that a dynamic power gain of 50% could be achieved while maintaining circuit frequency performance thanks to the use of efficient mobility boosters. Thus a clear scaling path to achieve high-mobility, power-efficient sub-14nm FDSOI technologies has been identified.

 

3.4: Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-Voltage Range SRAM Operation in 28nm UTBB FD-SOI

O. Thomas et al (UC Berkeley, ST)

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than 100fA/bitcell are measured in a 140kb programmable dynamic SRAM. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

 

27.5: New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration

C. Fenouillet-Beranger et al (Leti, ST, LASSE)

For the first time the maximum thermal budget of in-situ doped source/drain state-of-the-art FD-SOI bottom MOSFET transistors is quantified to ensure transistors stability in Monolithic 3D (M3D) integration. Thanks to silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Thanks to in-depth morphological and electrical characterizations, it shows very promising results for high performance Monolithic 3D integration.

 

9.2 Future Challenges and opportunities for Heterogeneous process technology. Toward the thin films, Zero intrinsic Variabiliiy devices, Zero power Era (Invited)

S. Deleonibus et al (Leti)

By 2025, 25 % of the World Gross Domestic Product will depend on the development of Information and Communication Technologies . Less greedy device, interconnect, computing technologies and architectures are essential to aim at x1000 less power consumption.

IBM’s SOI-FinFET, eDRAM and 3D Papers

32.1: Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme

H. Tsai et al (IBM)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision. In this paper, IBM researchers present the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node.

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

 

Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

 

3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News)

C-H. Lin et al (IBM)

The IBM team presents a fully integrated 14nm CMOS technology featuring FinFET architecture on an SOI substrate for a diverse set of SoC applications including high-performance server microprocessors and low-power ASICs. A unique dual workfunction process optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel and without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. Because the technology is envisioned for use in SoC applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom than ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

The SOI FinFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

 

16.1: First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications

P. Hashemi et al (IBM)

Strained SiGe FinFETs are a promising PMOS technology for the 10nm technology node and beyond, due to their excellent electrostatics and built-in uniaxial compression. Yet while SiGe FinFETs with moderate germanium (Ge) content have been characterized, little data exists on FinFETs with high Ge  content. And, what little data does exist is mostly focused on relaxed or strained pure Ge. For the first time anywhere, IBM detailed CMOS-compatible, low-power and high-performance SiGe PMOS FinFETs with more than 50% Ge content. The devices feature ultra-narrow fin widths – down to 3.3 nm – which provide excellent short-channel control for low-power applications.  Using a Si-cap-free passivation process, they report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1e13 cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. They demonstrated the highest performance ever reported (Ion=0.42mA/µm and Ioff=100nA/µm) for sub-20nm PMOS FinFETs at 0.5 V.

 

19.4: 0.026µm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications

C. Pei et al (IBM)

This paper presents the industry’s smallest eDRAM based on IBM’s 22nm (partially depleted) SOI technology, which has been recently leveraged for IBM’s 12-core 649mm2 Server Processor POWER8™. It summarizes the n-band resistance innovations, and reports for the first time the asymmetric embedded stressor, cavity implant and through gate implant employed in 22nm eDRAM technology. The fully integrated 256Mb product array has demonstrated capability of 1.4ns cycle time, which is significantly faster than any other embedded DRAM.

 

14.6: Through Silicon Via (TSV) Effects on Devices in Close Proximity– the Role of Mobile Ion Penetration – Characterization and Mitigation

C. Kothandaraman et al (IBM)

The research team identified and studied a new interaction between TSV processes and devices in close proximity, different from mechanical stress. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. They then presented an improved process, confirmed in test structures and DRAM.

 

RF-SOI

18.4: Technology Pathfinders for Low Cost and Highly Integrated RF Front End Modules

C. Raynaud (Leti)

This paper highlights the challenges related to the increasing number of modes (GSM, WCDMA, LTE) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multimode multi–band RF Front End modules.

 

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This is the 1st post in a 3-part series. Part 2 (click here to  read it) of ASN’s IEDM ’14 coverage looks at papers covering SOI-based future device architectures.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.