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What’s Behind the Power Savings in sureCore’s FD-SOI SRAM IP?

By Duncan Bremner, CTO SureCore Limited

Editor’s note: sureCore just announced availability of its 28nm FD-SOI memory compiler (press release here), which supports the company’s low-power, Single and Dual Port SRAM IP. Here, the company’s CTO explains why this IP is getting such impressive results.

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Recently, sureCore announced results from a 28nm FD-SOI test chip that showed dynamic power savings exceeding 75% and static power cuts up to 35% (when compared against a number of current commercial offerings), while only incurring a 5-10% area penalty for its ultra-low power SRAM IP.

And while this data is easily substantiated as shown in Figure 1, the sceptical industry pundits have raised questions that fall into two camps: (a) That can’t be done; or (b) How did they manage that? In answer to both of these questions, here’s a quick look at the history and engineering strategy that we adopted to deliver these results.

sureCore_FDSOI_power_comparison2

Figure 1: sureCore SRAM performance versus 5 leading IP suppliers.

Looking back to the early days of sureCore, SRAM fascinated us because despite many process iterations, the SRAM in use today bears a striking resemblance to the SRAM architectures that existed in the ’70s and ’80s. We concluded that no one had really taken a “blank-sheet-of-paper” look at the architecture for over 40 years. Recognising the growing importance of power efficiency for SoCs targeting forward-looking applications such as wearables, IoT, and other mobile devices, we examined power consumption in detail, and began by investigating how we could reduce SRAM power to a level attractive to the next generation of power critical, SoC designers.

Our starting point differed significantly from the traditional approach to SRAM R&D that typically starts at the bit cell. We recognised that the basic bit cell is fixed by the foundry; it’s a piece of electronics that is carefully optimised for fabrication. Modern bit cells are designed by the foundries who tend to put an emphasis on the broadest possible manufacturability drivers; yield and faster-time-to-volume as opposed to more performance-centric metrics. Their focus is on the front-end process optimisation, area and yield.

The basic rule of R&D fabless foundry engagement has been, “use the storage array – you won’t get a better packing density.” Consequently, the application use model had become separated from the technology — ‘faster or cheaper’ became the industry’s mantra instead of ‘faster and better’. This resulted in SRAM design teams focusing on how to build more sensitive read amplifiers to detect the signals, and better write amplifiers to drive the signal on to the bit cell. Not much time was spent looking at the fundamental architecture and asking: “Is this the best way?”

sureCore decided to take a more holistic view and stood back from the whole problem. We started with a clean sheet of paper and asked, “Where does the power go when you start storing data on SRAM?”

We discovered that a lot of the power is consumed hauling parasitic capacitance around. Our design strategy was therefore very simple; we developed a system architecture to optimize power while still retaining the area advantages of the standard foundry bit cell.

Simply stated, we architected the internal block architecture of SRAM by splitting the read amplifier function into a local and global read amplifier, thus dividing the capacitive load from the word-line, only driving the areas being addressed and not the whole array. This resulted in significant dynamic power savings during the read cycle. In a similar fashion, we reduced the write cycle power by a similar amount. Whilst hierarchical solutions are not new, the sureCore “secret sauce” is at circuit level developed by our engineering teams leading to not only significant power savings, but also comparable performance levels.

Our “blank sheet” approach delved deep; right down to the fundamental device physics level. Our strategic partners, Gold Standard Simulations — recognised world leaders in modelling devices at the atomic level and experts in nano-scale process nodes, helped us to understand the behaviour and limitations of processes at nodes below 28nm at a device level and bit cell level. Combining this fundamental device understanding with excellent circuit design and system analysis skills, we’ve identified where existing SRAM solutions waste power, and architected our solution to avoid this; we deliver power savings without the added complexity of write and read-assist.

At the outset, we determined it was important that our IP be process-independent. sureCore IP is based on architecture and circuit techniques rather than a reliance on process features. The result of this is technology that can reduce power in standard bulk CMOS, but is equally applicable to newer FinFET or FD-SOI processes and across all geometries, even down to 16nm and below. We believe our approach is paying off and, because we insisted in retaining the foundry optimised bit cell, sureCore’s technology can be retrofitted into existing designs enabling extended product life cycles.

This is our basic technology story… a start-up deciding to take a fresh look at an old technology and dramatically improving power performance over 75% compared with existing solutions. This is a new approach to SRAM power consumption for power sensitive applications and it delivers tangible battery life benefits to both the end user and the FD-SOI designers. Today’s FD-SOI technology is optimised for low power applications, bringing extended battery life to the nascent markets of wearables and IoT.

ByGianni PRATA

Call for submissions to FD-SOI IP Workshops (prizes!): Dresden (March), Bangalore (April), Shanghai (Sept), Grenoble (Dec)

 

Design & Reuse, in partnership with GlobalFoundries, ST, Soitec and Leti, is sponsoring a series of FD-SOI IP Workshops around the globe. (Click here for more information.) These working days aim at sharing information about IP that’s currently available or is being designed for FD-SOI technology.

The first conference will take place during DATE in Dresden on 14 March 2016. Following that, conferences will also be held in Bangalore in April, Shanghai in September, and Grenoble in December.

Short summary submissions are now being solicited from designers offering IPs that are either currently in validation, are already silicon-proven, or are in production. The deadline for submissions to the Dresden event is 15 February. A prize will be awarded to the most innovative IP.

FD-SOI specific design flow or module presentations are also welcome.

The organizers are all members of the European Things2Do program (read about that here), which includes about 50 partners working on the FD-SOI ecosystem.

ByAdministrator

Yes, 28nm FD-SOI Silicon Is Running (Samsung Interview, Part 1 of 3)

(New)Kelvin Low Portrait 2015

Kelvin Low, senior director of marketing for Samsung Foundry

Axel_Fischer_Samsung_28FDSOI_sm

Axel Fischer, director of Samsung System LSI business in Europe

ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.

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ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?

Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.

What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.

Samsung_28FDSOI_PDKS_12Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship

KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.

We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.

ASN: Do you have other customers lined up?

KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.

ASN: What about technology readiness and maturity?

KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.

Samsung_28FDSOI_process_costThis slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.

ASN: When will we see the first high-volume FD-SOI chips? Next year?

KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.

AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.

KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.

[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]

Samsung_28FDSOI_wafersAF: ST is our first partner for high-volume production. We started working together very early, so they have a time-to-market advantage.

KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.

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This is the first installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. Part 2 will cover design considerations, and Part 3 will look at the ecosystem.

ByAdministrator

Yes! FD-SOI IP Ready for GF, Samsung; Ecosystem Now a Force to Be Reckoned With

The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.

In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.

GF: 22 = 14 + 28

GF_FDSOIenablement_LetiDays15

(Courtesy: GlobalFoundries)

Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).

GF_FDSOI_LetiDays15_phases

Most of the challenges for delivering their 22nm FD-SOI offering have been met, said Gerde Teepe, Design Engineering Director at GF/Dresden.The final phase will be completed by the end of this year. (FD-SOI Workshop, LetiDays 2015)

The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.

IP, IP, IP

The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.

Samsung_FDSOI_design_LetiDays15

(Courtesy: Samsung)

Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.

Synopsys_FDSOI_IP_LetiDays15

Synopsys Senior Director Mike McAweeney explaining their Samsung IP strategy at the LetiDays ’15 FD-SOI Workshop.

This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.

IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.

Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)

Body Biasing Goes Adaptive

New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.

Hot Topic: Analog

Thurmann_analogFDSOI_design_LetiDays15

FD-SOI advantages for analog design include outstanding switch performance, said Boris Thurmann of Stanford. (LetiDays ’15)

In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.

FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.

FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.

Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.

You Gotta Believe

In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.

“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.

ST_Skotnicki_FDSOI_LetiDays15

(Courtesy: STMicroelectronics)

He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.

Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).

And clearly, he’s a man who knows the future.

ByAdministrator

Top Silicon Valley Companies Signed Up for FD-SOI & RF-SOI Forum (27 Feb. 2015 in SF, free, registration still open)

Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.

FDSOI_SF15_workshopIf you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.

Morning session: FD-SOI Workshop

FD-SOI foundry offer

  • FD-SOI Advantages for Applications and Ecosystem — Philippe Magarshack, CTO, STMicroelectronics
  • 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm — Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI
  • [Title TBA] — Jamie Schaeffer, GlobalFoundries

FD-SOI IP offer

  • Synopsys FD-SOI IP Solutions — Mike McAweeney, Sr. Director IP Product Sales, Synopsys
  • FD-SOI: Ecosystem and IP Design — Amir Bar-Niv, Senior Group Director, Product Management, Design IP, Cadence

FD-SOI design experience

  • [Title TBA] — N. Ben-Hamida, High speed Analog Design Manager, Ciena
  • 28nm FD-SOI Design/IP Infrastructure — Shirley Jin, Sr. Director of Engineering, Verisilicon

Panel discussion

Advantages and opportunities when designing with FD-SOIModerator: Dan Nenni, SemiWiki

Panelists:

  • Marco Brambilla, Director of Engineering, Synapse
  • Wayne Dai, Chairman, President & CEO, VeriSilicon
  • Kelvin Low, Sr Director, Foundry Marketing, Samsung SSI
  • Philippe Magarshack, CTO, STMicroelectronics
  • Guntram Wolski, Cisco Systems

Innovation

  • Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator — Mike Noonen, Chairman & Co-founder, Silicon Catalyst

Afternoon session: More than Moore Forum

  • RFSOI: Redefining Mobility and More in the Front-End – Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group
  • Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers — Barend Van Liempd, PhD Researcher, IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,)
  • RF SOI: from Material to ICs – an Innovative Characterization Approach — Mostafa Emam, CEO, Incize
  • ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration — Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics

If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.

This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.

For the SF event – here’s the key information:

FD-SOI and RF-SOI Forum

  • Friday, February 27th, 2015, 8am to 6pm
  • Palace Hotel
  • 2 New Montgomery Street, San Francisco, California, 94105 (USA)

The event is free but pre-registration is mandatory – click here to sign up on the SOI Consortium website.

ByGianni PRATA

On FD-SOI, Surecore’s ULP SRAM Saves 70% Power; Company Raised $1.6 Million (SemiEngineering)

SureCore’s ultra-low power SRAM technology on 28nm FD-SOI saves 70% in read/write power and reduces leakage by 30% compared to 40nm bulk implementations, writes SemiconductorEngineering Editor-In-Chief Ed Sperling (read the article here). Hitting the sweet spot for mobile, IoT and wearables, SureCore recently raised $1.6 million in funding.

ByGianni PRATA

ST video from IP-SoC on European FD-SOI ecosystem projects posted on YouTube

ST_FDSOI_ecosystem

(Courtesy: ST, designreuse)

A video made during ST’s FD-SOI presentation at IP-SoC 2014 has now been posted by designreuse on YouTube (you can see it here). Over 40 minutes long, it details the European THINGS2DO project, which includes almost 50 partners working on the FD-SOI ecosystem. (This follows onto the PLACES2BE project, which is finishing up this year.) It underscores the point that the markets for this ecosystem are very fragmented, so it’s critical that such an undertaking be as broad as possible.

ByAdministrator

Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too

The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide.  However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo.

In part 1 of ASN’s coverage of the workshop (click here if you missed it), we took a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis. Here in part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

Low Power SOC design with RF circuit by the FD-SOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Corporation

This presentation details Sony’s work on an 28nm FD-SOI version of its CXD5600GF Global Navigation Satellite System receiver LSI for smartphones and mobile products. When the bulk version was first released in 2013, the 10mW power consumption made it the industry’s lowest.  Now, with the 28nm FD-SOI version, they’ve gotten that down to a staggering 1mW – suitable for wearables. The presentation leads off by answering the question: Why FD-SOI? Sony engineers set themselves the challenge of a 0.6V target supply voltage for all logic, SRAM and analog (down from 1.1V in the previous generation). FD-SOI, especially leveraging body biasing, would enable them to attain this goal, providing a wide range of options for optimizing speed, power and area. The various steps and TEGs  (test element groups) are detailed in this presentation, and compared with 28nm and 40nm bulk. The advantages for low-power RF were particularly compelling.  This presentation has generated enormous attention in the press and in social media. For example, a week after EETimes published Sony Joins FD-SOI Club, it had been shared almost 200 times on LinkedIn.

Sony_Tokyo_FDSOI_GPS

(Courtesy: Sony)

 

Creation of high performance IP for FD-SOI by Kevin Yee, Director of Marketing, Cadence

As noted in this presentation, Cadence has existing solutions for 28nm FD-SOI, 14nm FD-SOI and 14nm FinFET-SOI. They have provided full design enablement for ST and Samsung processes. This presentation shows several examples of IP.

Cadence_Tokyo_FDSOI

(Courtesy: Cadence)

 

28nm FD-SOI Design/IP Infrastructure by Shirley Jin, Sr. Director of Engineering, VeriSilicon

Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. This presentation presents extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_Tokyo_28FDSOI_ARMbenchmark

Designing with FD-SOI – Benefits and Challenges by Huzefa Cutlerywala, Sr. Dir. Technical Solutions, Open-Silicon

Open-Silicon is a leader in traditional ASIC solutions, derivative and platform SoCs, hardware and software design and production handoffs. They are a channel partner for ST’s FD-SOI in Japan, have pipe-clean design flows for FD-SOI, and are currently taping out an FD-SOI test chip for a customer. They see FD-SOI as ideal for consumer and networking/telecom/storage/compute applications. This presention lists what they see as the benefits (which are impressive) and challenges (which are fairly minor), and provides some details on GPU and DSP cores.

OpenSilicon_Tokyo_FDSOI_DSPcore

(Courtesy: Open-Silicon)

 

Ultra Low Power Memory Solutions for FD-SOI by Paul Wells, CEO, SureCore

SureCore develops ultra-low power embedded SRAM IP. Making the point that memory typically dominates SoC area and can consume 70% of the power, SureCore sees FD-SOI as an elegant solution. Working samples of their SRAM solution in ST’s 28nm FD-SOI were received in March 2014, showing a 50% dynamic power savings, and high performance at low operating voltage. Extensive comparisons are given in this presentation.

Surecore_Tokyo_FDSOI_SRAM

(Courtesy: SureCore)

 

Synopsys FD-SOI IP Solutions by Mike McAweeney, Sr. Director, IP Product Sales, Synopsys

This presentation gives quite a detailed rundown of the ST-Synopsys 28FD-SOI IP program. Synopsys licenses a comprehensive, silicon-validated 28nm FD-SOI IP portfolio to Samsung’s foundry customers and other manufacturing partners. FD-SOI customers contract with Synopsys for standard Synopsys IP titles, with Synopsys customer support, part numbers, documentation and standard views. Slides 7 and 8 detail the commonly used interface, analog and display IPs available through Synopsys.

(Courtesy: Synopsys)

(Courtesy: Synopsys)

 

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

ByGianni PRATA

More FD-SOI myth-busting, courtesy semiwiki

In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI.  He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.

ByAdministrator

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know)

Following the big FD-SOI/EDA news, Synopsys has provided ASN with more details for designers.

Samsung_ST_logos             snps_logo

The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here).

They’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running. Samsung’s vice president of foundry marketing, Dr. Shawn Han, says, “28-nm FD-SOI is an ideal solution for customers looking for extra performance and power efficiency at the 28-nm node without having to migrate to 20-nm. Our close collaboration with Synopsys and ST will enable designers to reduce risk, accelerate time-to-market, minimize power and maximize performance to expand 28-nm FD-SOI adoption.”

Synopsys has collaborated closely with ST on FD-SOI for several years now – Galaxy is already successfully silicon-proven in several 28nm FD-SOI SoCs with multi-core processors, says the company. And just a few weeks ago, Synopsys announced that ST had standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization (see that press release here).

Synopsys says that the Galaxy Design Platform enables designers to take full advantage of FD-SOI’s low power and high performance. “Because the Galaxy Design Platform is silicon-proven on ST’s 28-nm FD-SOI process with multiple tapeouts of low power designs running in the gigahertz frequency range, customers can adopt this technology with confidence,” said Antun Domic, executive vice president and general manager, Design Group at Synopsys. “Combined with the Lynx Design System and DesignWare® IP, the Galaxy Design Platform enables engineers to derive maximum benefit from the FD-SOI process and our continued collaboration with ST and Samsung will ensure ease of adoption of FD-SOI for SoC design.”

The Galaxy Design Platform is a suite of design tools that work in an integrated way for design on both the digital and analog sides. It enables concurrent area, power and timing optimizations to enable engineers to optimize their designs for the ST 28nm FD-SOI process. Synopsys says the advanced design enablement features like the IC Compiler™ tool’s concurrent clock and data optimization, layer-aware optimization, physical datapath and comprehensive support for hierarchical and low-power design features can also be directly accessed by Lynx users for high-performance and low-power CPU and GPU design.

The Lynx Design System is an automation environment for chip designers. Lynx incorporates the full Galaxy Platform for both digital and analog implementation and for comprehensive design analysis. With technology portability and designer productivity as goals, the Galaxy flow in Lynx is architected technology independent. The accompanying technology plug-in structure enables design teams to quickly setup and implement on new technology nodes. Additionally, the automation architecture in Lynx enables the inclusion of third-party developed scripts and tools. Synopsys collaborates with the foundries to encapsulate technology-specific scripts and settings in the plug-in accelerating project setup and design time.

FD-SOI Specifics

Specifically for ST 28FDSOI, Synopsys collaborated with ST on the development of an ICC-Kit supporting UPF (Unified Power Format) and back-bias connections. Synopsys also implemented and validated a Lynx technology plug-in, integrating technology specific settings and scripts from the ICC-Kit into Lynx. The resulting combination significantly reduces designer overhead and implementation time for SOI nodes like ST 28FDSOI. Designers still need to add constraints and optimizations for their specific design, including the UPF files that specify the power intent. IC Compiler will connect the well ties and voltage converters in a manner consistent with the power-intent specified in the UPF Files (using scripts from the ICC-Kit).

All this should enable broader market adoption of ST’s 28nm FD-SOI technology for SoC design. “The close collaboration between ST design teams and Synopsys led to advanced silicon-proven design enablement solutions that fully leverage the performance and power promise of FD-SOI technology and provide the foundation needed to meet tight time to market windows,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics.

So there’s no need to wait. The Synopsys Galaxy Design Platform and Lynx Design System with support for ST and Samsung 28-nm FD-SOI process technology are available now from Synopsys. The 28-nm FD-SOI-enabled PDK, standard cells and memories for early design are available now from Samsung.

There’s no more doubt about it: for FD-SOI, it’s full speed ahead!

Note: Many thanks to Synopsys for help on the technical details in this piece.

ARM TechCon video/tutorial — recommended viewing:

ST_ARMCon_FDSOI_slide39
If you’re a designer looking for a good overview, there’s an excellent ARM TechCon 2013 video on FD-SOI posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market (he leads ST’s architecture activities for energy-efficient, high-performance CPU/GPU implementations). In his presentation (click on image above to view it) entitled, “Energy Efficient Implementation of ARM® Cortex©-A57/-A53 Processor Cores in FD-SOI Process Technology”, Jacquet begins with an overview of the FD-SOI process technology as an enabler for high-performance/low-power design. He then highlights the low-power implementation and verification methodology developed with Synopsys, including results and best practices.