Tag Archive low-power

Why NXP’s i.MX 7 and 8 Applications Processors are Taking on IoT, Wearables, Automotive and Other Embedded Markets with 28nm FD-SOI [Part 2 of 2]

By Ronald M. Martino, Vice President, i.MX Applications Processor and Advanced Technology Adoption, NXP Semiconductors

At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI.

As noted in part 1 of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable and IoT markets, where power efficiency is paramount. The i.MX 8 series leverages the 64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, and well as high-performance general embedded and advanced graphics applications.

Choosing an FD-SOI solution gave our designers some specific tools that helped them to more easily and robustly deliver the features our customers are looking for. Here in part 2, we’ll look a little more deeply into the markets each of these chip families is targeting, and the role FD-SOI plays in helping us meet our specs.NXProadmapFDSOIslide3

i.MX 7 Series: IoT, wearables and so much more

Announced last June, the first members of our new 7 series — the i.MX 7Solo and i.MX 7Dual product families — will be hitting the market shortly. We’ve been shipping samples since last year, and the response has been tremendous. (You can read about the i.MX 7 IoT ecosystem we’re helping create for our customers here and support for wearable markets here.)

Our i.MX 7 customers are building products for power- and cost-sensitive markets. That of course includes a vast array of innovative IoT solutions and wearables, but also solutions for other parts of the embedded market like handheld point-of-sale (POS) and medical devices, smart home controls and industrial products. The i.MX 7 series also continues NXP’s industry leading support for the e-reader market via integration of an advanced, fourth-generation EPD controller.NXPiMX7FDSOI

For all these markets, excellent performance is very important, but both dynamic and static power figures are really key. When you’re creating a system with power efficient processing and low-power deep sleep modes, you enable a new tier of performance-on-demand, battery-operated devices that are lighter and cheaper, and in a virtuous cycle require smaller batteries.

The next members of the NXP i.MX 7 series combine ultra-low power (dynamically leveraging the reverse back biasing you can do with FD-SOI) and performance-on-demand architecture (boosted when needed with FD-SOI’s forward back-biasing). It’s the industry’s first general purpose microprocessor family to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (customers can choose between single or dual A7 cores). These technologies, together with our new companion  PF3000 power management IC, unleash the potential for dramatically innovative, secure and power efficient end-products for wearable computing and IoT applications.

The initial offering of i.MX 7 was designed (on 28nm bulk) with Cortex-A7 cores operating up to 1 GHz, while the Cortex-M4 core operates at up to 200 MHz. The Cortex-A7 and Cortex-M4 achieve processor core efficiency levels of 100 microWatts (μW) /MHz and 70 μW /MHz respectively.

A Low Power State Retention (LPSR), battery-saving mode can be improved by FD-SOI and consumes only 250 μW, representing a 3x improvement over our previous generation (on 40nm bulk). That’s almost 50% better than our competitors. Plus it minimizes wake up times without requiring Linux reboot, while supporting DDR self-refresh mode, GPIO wakeup, and memory state retention.

NXPiMX7advFDSOIslide5The next members of the i.MX 7 series, with FD-SOI dynamic back-biasing, enable different blocks to be reverse or forward back-biased on the fly to attain always-optimal power savings or performance. Additional power optimization features are enabled to achieve leadership power efficiency. We’ve optimized FD-SOI dynamic back-biasing to enable performance-on-demand architecture through which the i.MX 7 series meets the bursty, high-performance needs (this is when forward back-biasing kicks in) of running Linux, graphical user interfaces, high-security technologies like Elliptic Curve Cryptography, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.

When high levels of processing are not needed, low-power modes kick in with reverse back biasing of the critical subsystems, and the ongoing, real-time work is carried on by the smaller, lower powered Cortex-M4.

All things considered, it’s perhaps no surprise that we expect i.MX 7 series solutions for cost-sensitive markets to be a key driver of our long-term i.MX portfolio expansion.

i.MX 8: Revolutionizing automotive, interactive multimedia/display apps

Our new i.MX 8 series portfolio, based on 28nm FD-SOI process technology, targets highly-advanced driver information systems and other multi-media intensive embedded applications. It incorporates those same key attributes as the i.MX 7, but extends them into realms the industry has never experienced. We believe the i.MX 8 series is poised to revolutionize interactivity in multimedia and display applications across all kinds of industries.

i.MX 8 incorporates innovations in the processor — complex graphics, vision, virtualization and safety to help revolutionize interactivity for a wide range of uses in many, many markets. The capabilities of this family is broad, but one of the places it’s going to be the biggest game-changer is in what is becoming the e-cockpit of your car.

For almost two decades, SOI has shone in the embedded processing world. In addition, NXP counts every major automotive maker in the world amongst its customers for our devices. Entering the new e-cockpit frontier, 28nm FD-SOI is the logical choice in making the i.MX 8 series meet and exceed the stringent requirements of top automotive OEMs for years to come.

The i.MX 8 series leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s. 
All the FD-SOI advantages discussed above for the i.MX 7 are also being brought to bear here (the power envelope for automotive designers being extremely strict). But in the hot and electrically noisy automotive environment, FD-SOI also plays an important role in ensuring robust operation.

NXPiMX8advFDSOIslide6The way we see it, your car’s multimedia centric e-cockpit will revolve around the i.MX 8, a single chip that drives all displays from infotainment to heads-up-displays (HUD) to instrument clusters. It’s optimized for the intelligent transfer of data and information management from multiple subsystems within the IC – as opposed to only delivering raw performance through one or two processing blocks.

For drivers and passengers alike, we’re looking at a very different world: one that includes the spread of advanced heads-up displays, intuitive gesture control, natural speech recognition, augmented reality, enhanced convenience and device connectivity. (I wrote a blog exploring the possibilities last fall – you can read it here.)

And of course, it will be secure from hackers, and fail-safe for critical systems.

From our customers’ standpoint, they can design a single hardware platform and scale it across multiple market segments with the unique approach to pin and software compatibility within the i.MX product families.

The i.MX family has been leveraged in over 35 million vehicles since it was first launched in vehicles in 2010. So with all these new features, and low-power and robust performance, we see a very bright future for FD-SOI and the i.MX 8 in automotive. It’s going to be a great ride.

NXP’s Latest i.MX Applications Processors for IoT/Wearables and Automotive – Here’s Why They’re on FD-SOI [Part 1 of 2]

By Ronald M. Martino, Vice President, i.MX Applications Processor and Advanced Technology Adoption, NXP Semiconductors

The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where power efficiency is paramount. The i.MX 8 series leverages the 64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications.

Over 200 million i.MX SOCs have been shipped over six product generations since the i.MX line was first launched (by Freescale) in 2001. They’re in over 35 million vehicles today, are leaders in e-readers and pervasive in the general embedded space. But the landscape for the markets targeted by the i.MX 7 and i.MX 8 product lines are changing radically. While performance needs to be high, the real name of the game is power efficiency.

Why are we moving to FD-SOI?

The bottom line in chip manufacturing is always cost. A move from 28nm HKMG to 14nm FinFET would entail up to a 50% cost increase. Would it be worth it? While FinFETs do boast impressive power-performance figures, for applications processors targeting IoT, embedded and automotive, we need to look beyond those figures, taking into account:

  • when and how performance is needed and how it is used;
  • when power savings are most pertinent;
  • how RF and analog characteristics are integrated;
  • the environmental conditions under which the chip will be operating;
  • and of course the overall manufacturing risks.

In fact, both NXP and the former Freescale have extremely deep SOI expertise. Freescale developed over 20 processors based on partially-depleted SOI over the last decade; and NXP, having pioneered SOI technology for high-voltage applications, has dozens of SOI-based product lines. So we all understand how SOI can help us strategically leverage power and performance. For us, FD-SOI is just the latest SOI technology, this time with a design flow almost identical to bulk, but on ultra-thin SOI wafers and some important additional perks like back-biasing.

When all the factors we care about for the new i.MX processor families are tallied up, FD-SOI comes out a clear winner for i.MX SOCs.

FD-SOI: Designing for Power, Performance and more

For our designers, here’s why FD-SOI is the right solution to the engineering challenges they faced in meeting evolving market needs.

In terms of power, you can lower the supply voltage (Vdd) – so you’re pulling less power from your energy source – and still get excellent performance. Add to that the dynamic back-biasing techniques (forward back-bias improves performance, while reverse back-bias reduces leakage) available with FD-SOI (but not with FinFETs), you get a very large dynamic operating range.FDSOIslideadvtg1NXP

By dramatically reducing leakage, reverse back-biasing (RBB) gives you good power-performance at very low voltages and a wide range of temperatures. This is particularly important for IoT products, which will spend most of their time in very low-power standby mode followed by short bursts of performance-intense activity. We can meet the requirements for those high-performance instances with forward back-biasing (FBB) techniques. And because we can apply back-biasing dynamically, we can specify it to meet changing workload requirements on the fly. [Editor’s note: click here and here for helpful ASN articles with descriptions and discussions of back-biasing, which is also sometimes called body-biasing.]

Devices for IoT also have major analog and RF elements, which do not scale nearly so well as the digital parts of the chip. Furthermore analog and RF elements are very sensitive to voltage variations. It is important that the RF and analog blocks of the chip are not affected by the digital parts of a chip, which undergo strong, sudden signal switching. The major concerns for our analog/RF designers include gain, matching, variability, noise, power dissipation, and resistance. Traditionally they’ve used specialized techniques, but FD-SOI makes their job much easier and results in superior analog performance.

In terms of RF, FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example, into an SOC.

Soft error rates (SER)* are another important consideration, especially as the size and density of SOC memory arrays keep increasing. Bulk technology gets worse SER results with each technology node, while FD-SOI provides ever better SER reliability with each geometry shrink. In fact, 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart.

Our process development strategy has always been to leverage foundry standard technology and adapt it for our targeted applications, with a focus on differentiating technologies for performance and features. We typically reuse about 80% of our technology platform, and own our intellectual property (IP). Looking at the ease of porting existing platform technology and IP, and analyzing die size vs. die cost, again, FD-SOI came out the clear choice.FDSOIslide2costNXP

In terms of manufacturing, FD-SOI is a lower-risk solution. Integration is simpler, and turnaround time (TAT) is much faster. 28nm FD-SOI is a planar technology, so it’s lower complexity and extends our 28nm installed expertise base. Throughout the design cycle, we’ve worked closely with our foundry partner, Samsung. They provided outstanding support, and very quickly reached excellent yield levels, which is of course paramount for the rapid ramp we anticipate on these products.

In the second part of this article, we’ll take a look at the new i.MX product lines, and why FD-SOI is helping us make those game-changing plays for specific markets.

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* Soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.

Reminder re: top SOI Conference – IEEE S3S ’16 (SOI/3D/SubVt) CFP deadline April 15th. Keynotes: NXP, Skyworks, Qualcomm

S3SconflogoDon’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.

As of this writing, the following keynote speakers have been confirmed:

  • Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
  • Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
  • Nick Yu, Qualcomm : topic TBAieee_logo_mb_tagline

Invited speakers include:

  • Jamie Schaffer, GlobalFoundries : topic TBA
  • Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
  • Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
  • Xavier Garros, CEA-Leti : “Reliability of FDSOI”

As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.

Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :

  • SOI
  • 3D Integration
  • Subthreshold MicroelectronicsEDS-Logo-Reflex-Blue-e1435737971222

For current information on the conference visit the S3S website at: http://s3sconference.org/

LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.

What’s Behind the Power Savings in sureCore’s FD-SOI SRAM IP?

By Duncan Bremner, CTO SureCore Limited

Editor’s note: sureCore just announced availability of its 28nm FD-SOI memory compiler (press release here), which supports the company’s low-power, Single and Dual Port SRAM IP. Here, the company’s CTO explains why this IP is getting such impressive results.

~ ~ ~

Recently, sureCore announced results from a 28nm FD-SOI test chip that showed dynamic power savings exceeding 75% and static power cuts up to 35% (when compared against a number of current commercial offerings), while only incurring a 5-10% area penalty for its ultra-low power SRAM IP.

And while this data is easily substantiated as shown in Figure 1, the sceptical industry pundits have raised questions that fall into two camps: (a) That can’t be done; or (b) How did they manage that? In answer to both of these questions, here’s a quick look at the history and engineering strategy that we adopted to deliver these results.

sureCore_FDSOI_power_comparison2

Figure 1: sureCore SRAM performance versus 5 leading IP suppliers.

Looking back to the early days of sureCore, SRAM fascinated us because despite many process iterations, the SRAM in use today bears a striking resemblance to the SRAM architectures that existed in the ’70s and ’80s. We concluded that no one had really taken a “blank-sheet-of-paper” look at the architecture for over 40 years. Recognising the growing importance of power efficiency for SoCs targeting forward-looking applications such as wearables, IoT, and other mobile devices, we examined power consumption in detail, and began by investigating how we could reduce SRAM power to a level attractive to the next generation of power critical, SoC designers.

Our starting point differed significantly from the traditional approach to SRAM R&D that typically starts at the bit cell. We recognised that the basic bit cell is fixed by the foundry; it’s a piece of electronics that is carefully optimised for fabrication. Modern bit cells are designed by the foundries who tend to put an emphasis on the broadest possible manufacturability drivers; yield and faster-time-to-volume as opposed to more performance-centric metrics. Their focus is on the front-end process optimisation, area and yield.

The basic rule of R&D fabless foundry engagement has been, “use the storage array – you won’t get a better packing density.” Consequently, the application use model had become separated from the technology — ‘faster or cheaper’ became the industry’s mantra instead of ‘faster and better’. This resulted in SRAM design teams focusing on how to build more sensitive read amplifiers to detect the signals, and better write amplifiers to drive the signal on to the bit cell. Not much time was spent looking at the fundamental architecture and asking: “Is this the best way?”

sureCore decided to take a more holistic view and stood back from the whole problem. We started with a clean sheet of paper and asked, “Where does the power go when you start storing data on SRAM?”

We discovered that a lot of the power is consumed hauling parasitic capacitance around. Our design strategy was therefore very simple; we developed a system architecture to optimize power while still retaining the area advantages of the standard foundry bit cell.

Simply stated, we architected the internal block architecture of SRAM by splitting the read amplifier function into a local and global read amplifier, thus dividing the capacitive load from the word-line, only driving the areas being addressed and not the whole array. This resulted in significant dynamic power savings during the read cycle. In a similar fashion, we reduced the write cycle power by a similar amount. Whilst hierarchical solutions are not new, the sureCore “secret sauce” is at circuit level developed by our engineering teams leading to not only significant power savings, but also comparable performance levels.

Our “blank sheet” approach delved deep; right down to the fundamental device physics level. Our strategic partners, Gold Standard Simulations — recognised world leaders in modelling devices at the atomic level and experts in nano-scale process nodes, helped us to understand the behaviour and limitations of processes at nodes below 28nm at a device level and bit cell level. Combining this fundamental device understanding with excellent circuit design and system analysis skills, we’ve identified where existing SRAM solutions waste power, and architected our solution to avoid this; we deliver power savings without the added complexity of write and read-assist.

At the outset, we determined it was important that our IP be process-independent. sureCore IP is based on architecture and circuit techniques rather than a reliance on process features. The result of this is technology that can reduce power in standard bulk CMOS, but is equally applicable to newer FinFET or FD-SOI processes and across all geometries, even down to 16nm and below. We believe our approach is paying off and, because we insisted in retaining the foundry optimised bit cell, sureCore’s technology can be retrofitted into existing designs enabling extended product life cycles.

This is our basic technology story… a start-up deciding to take a fresh look at an old technology and dramatically improving power performance over 75% compared with existing solutions. This is a new approach to SRAM power consumption for power sensitive applications and it delivers tangible battery life benefits to both the end user and the FD-SOI designers. Today’s FD-SOI technology is optimised for low power applications, bringing extended battery life to the nascent markets of wearables and IoT.

GlobalFoundries and Synopsys Streamline the Move to 22nm FD-SOI

By: Tamer Ragheb, Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys

It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT).

GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 1_Benefits of 22FDX body-biasing

Figure 1: Benefits of 22FDX body-biasing

The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 2_22FDX Body Bias Optimizes Performance and Power

Figure 2: 22FDX Body Bias Optimizes Performance and Power

In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include:

  • Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance
  • Low variability and body-biasing capability that can achieve 0.4 volt operation
  • Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent

Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs.

There are four application optimized extensions available with 22FDX (Fig. 3). These are:

  • 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation.
  • 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage.
  • 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications.
  • 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications.
GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 3_22FDX Platform and Extensions

Figure 3: 22FDX Platform and Extensions

GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications.

GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.

Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include:

  • Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization
  • Formality® formal verification with bias-aware equivalence checking
  • IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology
  • IC Validator In-Design physical verification

The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.

GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

GFwebsiteFDXintro

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

15-GFwebinarSept28_FDX_ULPSOCex

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

GFwebsiteFDXJulyWebinarPPcost

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

S3Sadvprgmpic_lowres

Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

S3S15lineup

The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

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Find all the details about the conference on our website: s3sconference

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S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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FinFET or FD-SOI? Designers have a real choice, say experts

Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.

Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.

But is that really where most designs are?

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.

Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.

EDA experts weigh in at EDPS

Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.

EDPSlogoThe session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.

And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”

EDPS_FF_FDSOI_panel

EDPS 2015 panelists debate FinFET vs. FD-SOI. (Left to right: Marco Brambilla (Synapse Design); Kelvin Low (Samsung); Boris Murmann (Stanford); Jamie Schaeffer (GlobalFoundries). (Image courtesy: Richard Goering and Cadence)

In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:

  • Kelvin Low, Sr. Director Foundry Marketing for Samsung
  • Boris Murmann, Stanford professor and analog/mixed-signal expert
  • Marco Brambilla, Director of Engineering at Synapse Design
  • Jamie Schaeffer, Product Line Manager at GlobalFoundries

The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”

There you have it!

Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.

Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).

Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.

So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.

 

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

SatishBagalkotkar_outside

Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.

ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.

Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?

Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.

ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?

SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.synapse_logo_300_ppi

ASN: At what point in the design process do you typically come in? What sorts of services do you offer?

SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.

ASN: What do you see as the advantages of FD-SOI?

SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.

SynapseDesign_FDSOI_v_bulk

An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.

We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.

ASN: Designers of what kinds of chips should be thinking about FD-SOI?

SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.

ASN: Why do they ultimately choose it? Why do they hesitate?

SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.

ASN: Are there special considerations designers should think about before starting a project in FD-SOI?

SynapseDesign_FDSOI_diffSB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.

ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?

SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.

Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.

ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?

SynapseDesign_FDSOI_summarySB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market

ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?

SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.

ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?

SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.

We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.

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Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.