Tag Archive manufacturing

ByAdele Hars

Customer demand drives Soitec launch of FD-SOI wafer pilot line in Singapore

SOI wafer leader Soitec is launching a pilot line to produce FD-SOI wafers in its Singapore wafer fab (press release here). This is the first stage in beginning FD-SOI production in Singapore and providing multi-site FD-SOI substrate sourcing to the global semiconductor market.

“Our decision to launch this FD-SOI line in Singapore as well as the decision we already made to ramp up our FD-SOI production in France are based on direct customer demand,” said Paul Boudre, CEO of Soitec. “These are very important milestones for Soitec and the expanding FD-SOI ecosystem. In Singapore, we plan to get full qualification at the customer level in the first half of 2019 and then increase capacity in line with market commitment.”

Soitec reports that its investment in Singapore to launch its FD-SOI pilot line is approximately US$40 million, to be spent over a 24-month period.

ByAdele Hars

Samsung Certifies Synopsys Custom Design Platform for 28nm FD-SOI

Custom Compiler visually-assisted automation flow. (Courtesy: Synopsys)

Synopsys’ custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE® golden-accuracy circuit simulation, Custom Compiler visually-assisted layout automation, StarRC gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT, connectivity, mobile computing and automotive. (Read the full press release here.)

“Samsung Foundry’s certification of Synopsys’ custom design platform is important to our mutual customers developing complex designs,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity.”

Custom Compiler’s user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS PDK in the industry-standard interoperable (iPDK) format.

“Samsung Foundry’s 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “We worked with Synopsys to certify Synopsys’ custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development.”

ByAdele Hars

$100M+ investment for FDX™ FD-SOI Chengdu design center of excellence

(Source: Google Maps)

GlobalFoundries  and the Chengdu municipality plan to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. They’ve announced an investment of more than $100 million, which is expected to attract leading semiconductor companies to Chengdu, making it a center of excellence for designing next-generation chips in mobile, IoT, automotive and other high-growth markets.

This follows hard on the heels of the partners’ announcement that they’re building a 300mm fab in Chengdu to meet accelerating global demand for GF’s 22FDX® FD-SOI technology.

The partners’  plan is to establish multiple centers focused on IP development, IC design and incubating fabless companies in Chengdu, with the expectation of hiring more than 500 engineers to support semiconductor and systems companies in developing products using 22FDX for mobile, connectivity, 5G, IoT, and automotive. There will also be a focus on creating partnerships with universities across China to develop relevant FD-SOI coursework, research programs and design contests.

Support for the plan is pouring out from across the ecosystem (read the press release here for all the quotes).

“This new design and IP ecosystem in Chengdu is exactly what the Chinese fabless industry needs to take advantage of the game-changing features of FD-SOI, ” says Dan Hutcheson, CEO and Chairman of VLSI Research.  “The initiative is well positioned for success, considering GF’s track record of positive private-public partnerships to grow ecosystems around its fabs in Germany and New York.”

 

 

 

ByAdele Hars

Upcoming SOI/FD-SOI Workshop in Tokyo – Great Line-Up, Registration Still Open

Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.

This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.)  You’ll find the full program here. A brief summary follows.

(©Tokyo Convention & Visitors Bureau)

Day 1

The first day – Wednesday, May 31st  – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.  

It will take place on the 25th floor of the Yokohama Landmark Tower.  The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.

Day 2

The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.  

It kicks off with talks on ultra-low power applications from Sony IoT and Samsung.  Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure.  The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.

Coffee breaks and lunch will give attendees and speakers time for further discussion.

This is a great opportunity – don’t miss it!

ByAdele Hars

Part 2: NXP’s new i.MX 7ULP – More on Why It’s On 28nm FD-SOI

i.MX 7ULP (Courtesy: NXP)

As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.

If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)

To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:

  • Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.

  • Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.

  • Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.

  • Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.

  • Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.

  • RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.

  • Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.

  • Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.

  • Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.

But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”

Next up: i.MX 8 for automotive +

At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.

We’ll cover it in an upcoming ASN blog, so stay tuned!

— By Adele Hars, ASN Editor-in-Chief

ByAdele Hars

GF FD-SOI: Fab for China, Expansion in Europe

SOI Consortium member GlobalFoundries is teaming up with the Chengdu municipality to build a fab in western China offering FD-SOI (see press release here). The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX®, GF’s 22nm FD-SOI process technology. The Chengdu fab is expected to begin volume production of 22FDX in 2019.

In Germany, GF plans to grow the overall FD-SOI capacity of its Fab 1 facility in Dresden by 40 percent by 2020.  GF says they need the new capacity to meet demand for IoT, smartphone processors, automotive electronics, and other battery-powered wirelessly connected applications. Dresden will continue to be the center for FDX technology development. GF engineers in Dresden are already developing the company’s next-generation 12FDXTM technology, with customer product tape-outs expected to begin in the middle of 2018.

In Singapore, GF will also add new capabilities to its industry-leading RF-SOI technology.

ByAdele Hars

FD-SOI/Shanghai Forum – Panel Sees Great Things Coming

shanghaifdsoi2016

Shanghai FD-SOI Forum Panel Discussion (left to right): Wayne Dai, CEO Verisilicon (moderator); Marshal Cheng, SVP Leadcore; Mahesh Tirupattur, EVP Analog Bits; Subramani Kengeri, VP GlobalFoundries; Handel Jones, CEO IBS; Christophe Maleville, VP Soitec. (Photo courtesy SOI Consortium and Verisilicon)

The panel discussion rounding out the day at the recent FD-SOI Forum in Shanghai ended an exciting week (GF’s 12nm FD-SOI & ecosys, Sony’s FD-SOI GPS in the Huami watch) on a decidedly optimistic note. Here’s a quick rundown of some of what was said.

(As soon as the presentations given earlier in the day are posted, we’ll take a quick cruise through those, too.)

Anything IOT is better on FD-SOI

Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits started it off with the reminder that for anything “always on” in IoT, FD-SOI’s always better. They had a terrific experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here). The port from 28 bulk took 2 1/2 months (vs. to FinFET, which took almost 6). Even without using body bias, they got performance up by around 15% and leakage down by about 30% (he added that with body bias, they could get five times that).

He compared porting to FD-SOI to playing high school ball, vs. a port to FinFET which is like competing in the Olympics. ESD was different, but not a big deal – you just need to “read the manual”. Heating? Nothing an engineer can’t resolve. For IoT, FinFETs are like using a cannon to shoot a mosquito, he quipped.

He later ticked off a few more advantages of FD-SOI for the IoT design community: system cost, lower power – and here’s a particularly interesting observation – cheaper packaging. They were able to do wire bonding, so they were able to package a wearable video app in a plastic capsule. All things considered, FD-SOI offers the perfect solution, he said (and now he’s got silicon with “dramatic results” to prove it), adding that the IP guys need to evangelize this.

Moving really fast

GloFo VP Subramani Kengeri took a moment to look back before he looked forward. “FD-SOI is not new,” he reminded us. It was explored and researched for a decade. But at the beginning, CPUs were driving the industry, and everyone else followed suite. But now in mobile and IoT, RF is becoming more important, and what was good for the CPU is no longer what’s good for everything else. He tipped his hat to Soitec, ST and Leti, who “kept the lights on” and kept driving FD-SOI forward. Now with 5G on the horizon, FD-SOI is the enabler, he added.

He also noted that FD-SOI gets you the maximum memory onchip, and that with 12FDX, we’ll be seeing the world’s smallest SRAM. So that opens a new degree of freedom. The EDA partners have been working on automating body bias in the PDK for greater power management. He cites an ARM core with on-demand performance that can be used “intelligently”. Is it complicated? Not really, he says, especially if it’s automated. In fact he sees body bias opening the market for “extraordinary, innovative products” very soon. Key IP is in place. And it’s not just for IoT: aside from high-end CPUs, FD-SOI is optimal for everything. “Everything’s happening now, and it’s moving really fast,” he said.

Clear substrate path to 7nm

SOI wafer leader Soitec VP Christophe Maleville was asked if he saw any limit on manufacturing the ultra-thin wafers for the 7nm node. No problem, he said – they can do those wafers with 4nm of strained top silicon and a 10nm layer of insulating BOX. They’ve been working on FD-SOI wafers for over a decade, he reminded us, with Leti, IBM and ST. Back in 2013 when ST announced the Nova-Thor hitting 3GHz (or 1GHz at just 0.6V), everything was in place: the metrology was ready, reliability was controlled.

Today they’ve got a 15nm BOX layer in manufacturing, with no limits in moving to 10nm for customers going for very low power. For the strained top silicon needed for the 7nm node, they spent years working on strain with IBM et al in Albany, so they’re not starting from scratch. That substrate will be mature in just two years, so from a substrate point of view, he said, “7nm is no problem”.

Coming fast: lots of products (and a fab for China?)

In response to a follow-up question from a well-known analyst in the China tech industry, panel moderator and Verisilicon CEO Wayne Dai said that the design community in China has the skills to do FD-SOI, no problem. He’d like to see more IP, but FD-SOI has powerful advantages in terms of cost, analog/memory and back biasing.

Dai then asked the panelists if they thought we’d be seeing a foundry in China opting for FD-SOI by next year – all but one said yes. One thing all the panelists agreed on, however: they all expect to see FD-SOI products (and lots of them) on the stage at the Shanghai FD-SOI forum in 2017.

ByAdele Hars

Why Dan Hutcheson/VLSIresearch, Inc. (finally!) Likes FD-SOI

Dan Hutcheson, CEO of VLSIresearch, Inc. finally likes FD-SOI. That’s important, because he’s a really influential person in the chip world. Everybody who’s anybody in the chip biz pays attention to what VLSIresearch, Inc. has to say.

Dan recently gave a talk entitled “FD-SOI: Disruptive or Just Another Process?” to a packed-to-the-brim room during the FD-SOI Symposium in San Jose. (The ppt he used there is available on the SOI Consortium website – download it for free here).

DanHutchesonVideopicHappily for those who didn’t make it to San Jose, Dan then went into the studio and made a video encore of his presentation for all to see – and it’s now posted on his weSRCH site. So you get not just his slides, but also his explanations and comments.

It’s about 20 minutes long – and worth every second. (Recommendation: open the ppt presentation (link here) and the video (link here) in separate windows so you can follow his slides as he talks.)

But for those of you who just want a quick recap, here are some of his key points.

He Did A Survey

Dan, as he’s always quick to point out, is an economist, albeit one extremely well-versed in chip technology. He always thought SOI was an elegant solution, but didn’t see cost savings in the fab as a driver. When asked to give a talk in San Jose, he decided to brush up a bit on what people were saying about FD-SOI. So he did an informal survey – and of course, being Dan, he can talk to just about anyone he wants.

In this case, he talked to decision makers from about a dozen top companies in the chip biz – enough to give him a 95% confidence level in his results. And the results are impressive: almost ¾ said they had FD-SOI designs underway or had already used it, while only about a third said they’ll stick firmly to bulk.

And Found That It’s About Time-to-Money

It turns out that there are companies out there doing both FinFETs and FD-SOI. Why? They’ve figured out the differentiable features, they told him. And some designers are now saying that FD-SOI is actually easier to design in than FinFETs, with one company reporting that design time in FD-SOI was half that of FinFETs.

Dan learned that the two biggest drivers of FD-SOI are IoT and automotive – IoT because those super power-stingy chips get enormous leverage out of back biasing, and automotive for reliability (and for both they get ease of analog integration).

VLSIResearch_FDSOI_markets_SJslide16

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

But at the heart of it, it’s a business case: “It’s not about cost,” he says. “It’s about time-to-money.” With FD-SOI, TTM is significantly faster.

VLSIresearch_FDSOI_bizcase_SJ2016

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

Those that go with FinFET are more often a big company (so they can afford the high NRE* costs) with a huge market, big die and a lot of digital. But if the market’s smaller, faster-moving and needs scaled-down NRE costs, then the people Dan talked to said they are turning to FD-SOI. They see it getting them to market faster, gives them lots of “knobs” and advantages in terms of power, reliability and analog integration, it’s easier to design in, and really enables product differentiation. In fact Dan had analog folks telling him that FD-SOI gave them back some of their favorite tricks and tools that they’d lost after the 130nm node.

(Courtesy: VLSIresearch and SOI Consortium)

(Courtesy: VLSIresearch, Inc. and SOI Consortium)

Finally, Dan sees FD-SOI as a technology with both a long history and a long lifetime ahead. FD-SOI is not in itself disruptive, but is rather an enabler of disruption. The disruption, he says, is IoT. By all means check out his video if you want more detail on his perspective on IoT, automotive and the foundry offerings.

 In conclusion, he urges users to strengthen the ecosystem’s momentum by disclosing their success stories – though he also sees how they might be reluctant to, as FD-SOI is the secret sauce that gives them a huge competitive advantage. But in the end rewards will be reaped, as driving volume up will drive costs down.

If you have a good FD-SOI design story you’d like to share, let us know here at ASN – we’ll be happy to consider it for publication, to help get the word around.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).

 

 

 

 

ByGianni PRATA

Use 28nm FD-SOI, Samsung advises new customers and designers (SemiEngineering)

“We intend to focus all new engagements in design using 28nm FD-SOI,” Samsung Semi’s Kelvin Low told SemiEngineering’s Mark Lapedus in a recent article (read it here).

Low, who’s senior directory of the company’s foundry marketing says they’ll of course continue to support existing 28nm bulk customers, “But we think FD-SOI has enough benefits to attract new customers and designers.”

 

ByAdele Hars

San Jose Symposium – Part 2 of 2 in an Epic Day for FD-SOI – the “Disruption Enabler” Right Through 7nm

This is part 2 (of 2) of ASN’s coverage of the epic FD-SOI Symposium in San Jose. In part 1 we looked at the exciting developments happening at 28nm (if you missed it, click here to read it now). Here in part 2, we’ll look at 22nm, covering the presentations by GlobalFoundries, ARM, VLSI Research and Sigma Designs. Again, the presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).

VLSI Research – FD-SOI is Enabler of Disruption

Dan Hutcheson, CEO of VLSI Research, has come around to FD-SOI. His excellent talk, “FD-SOI: Disruptive or Just Another Process” (click here to download it), concluded that FD-SOI is not disruptive – but it’s an enabler of disruption. The disruption is IoT, and it’s going to be a big one. To prepare for his talk, he did an informal survey of designers at a dozen top companies. Here are some of the things he heard:

  • Some companies are using FinFET for some chips and FD-SOI for others, depending on the market they’re targeting – either way, the technologies will co-exist. FinFETs were generally chosen for high-density chips from large companies with lots of money; FD-SOI by those who have time-to-market constraints, are looking to differentiate their products, appreciate the much lower NRE* costs, and that are going for power, reliability and analog advantages.

  • People see a future with FD-SOI – it’s not a one-trick process.

  • The design community is happy to be able to re-use many of their favorite techniques that were lost after the 130nm node.

  • Top target markets for FD-SOI are (by far) IoT, automotive and low-power, followed by analog/mixed-signal, networks, RF, low-end products, mobile, peripherals, MPU/GPU, image sensors and rad-hard.

Here are a couple of his slides that sum up the technical and business reasons people cited as reasons for going to FD-SOI:

(Courtesy: VLSI Research and SOI Consortium)

(Courtesy: VLSI Research and SOI Consortium)

Dan then made a video recapping his San Jose presentation – it’s awesome – click here to see it.

GlobalFoundries – Full House

The ballroom packed right out when GloFo VP Subramani Kengeri took the stage to present, “Enabling Next Generation Semiconductor Product Innovations with 22FDXTM.

The ballroom packed right out when GloFo VP Subramani Kengeri took the stage at the FD-SOI Symposium in San Jose. (photo credit: Adele Hars)

The ballroom packed right out when GloFo VP Subramani Kengeri took the stage at the FD-SOI Symposium in San Jose. (photo credit: Adele Hars)

In terms of energy efficiency, he explained, 0.4V is the minimum energy point for almost any technology – and FD-SOI gets you 0.4V. He then went on to reiterate the features of GloFo’s 22FDXTM Platform, the industry’s first 22nm FD-SOI:

  • Ultra-lower power with 0.4 volt operation

  • Software-controlled transistor body-biasing for innovative performance and power optimization

  • Delivers FinFET-like performance and better energy-efficiency at 28nm-like cost

  • Integrated RF: reduced system cost, and back-gate feature to reduce RF power up to ~50%

  • Integrated eNVM and RF enables lowest cost and smallest form-factor

  • Post-Silicon Tuning/Trimming for Analog/RF, SRAM and Power/Performance optimization

  • Enables innovative applications across mobile, IoT and RF markets

  • 70% lower power than 28HKMG, 20% smaller die than 28nm bulk planar

  • Lower die cost than FinFETs

He then gave lots of technical details (the whole presentation is now available for download from the SOI Consortium website – click here to get it). A key point is that FD-SOI will scale to 7nm. Here’s the slide that says it all:

(Courtesy: GlobalFoundries and SOI Consortium)

(Courtesy: GlobalFoundries and SOI Consortium)

Also, be sure to check out the Cadence presentation when it’s posted – it looks at the solid design methodology now in place.

ARM – now onboard!

Following a brief mea culpa acknowledging that ARM had been missing too long from the FD-SOI table, GM of the Physical Design group Will Abbey made it clear that they are now fully onboard. In his talk, “Realize the Potential of FD-SOI”, he said in comparisons between 22nm FD-SOI and 14nm FinFET, they see a lot of space for FD-SOI. Here’s his summary slide:

(Courtesy: ARM and the SOI Consortium)

(Courtesy: ARM and the SOI Consortium)

They are now looking at ways to further optimize back-biasing to decrease total power in block-level implementations. And yes, he said, you’ll get performance that’s close to FinFET.

Sigma Designs – IoT

Fabless innovator Sigma Designs is focused on the connected home (especially smart TV and media connectivity) and IoT. CEO Thinh Tran presented, “Enabling the Digital Connected World with FDSOI” – you can download it here.

If you really want to optimize for power efficiency, use FD-SOI and run at 0.4V, he advised. “I’m very excited about this,” he told the San Jose audience, adding that, “It’s especially good for RF.” Here’s his slide that explains why:

(Courtesy: Sigma Designs and SOI Consortium)

(Courtesy: Sigma Designs and SOI Consortium)

So, it was a great day in San Jose for 22nm and 28nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).