Samsung Adding eFlash and eMRAM Options to 28nm FD-SOI (EETimes)

Samsung is adding two embedded NVM (non-volatile memory) options to its 28nm FD-SOI line-up, Kelvin Low told EETimes‘ Peter Clark in a recent interview (read the whole piece here). Low, who heads up marketing and bizdev for Samsung Foundry, indicated the following roll-out for 28nm FD-SOI: eFlash – risk production by the end of 2017; […]

Leti’s M3D, now dubbed “CoolCube”, featured in EETimes

Leti’s monolithic 3D technology, which has now been dubbed “CoolCube”, was featured in a recent EETimes piece.  Entitled True 3D monolithic integration eliminates TSV dependence (click here to read it), the article covers a Leti paper presented during a 3D-VLSI workshop preceding IEDM ’14.  Leti’s Advanced CMOS lab manager Maud Vinet detailed the “cool” process in […]

Two additions to Altatech equipment lines: 10x faster ultra-thin film deposition; Doppler nano-defect inspection captures true sizing and positioning

Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies […]

ST presents silicon R&D results on hafnium memory technology for FD-SOI MCUs

Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate […]

New SOI Textbook (and e-book) with contributions by experts at Soitec, GF, TSMC, Leti and more

A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more. Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore.  It goes into SOI wafer technology,  […]

IP for FD-SOI: Examples from ST

Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

SOI Pioneers Mazure and Raskin Join Ranks of IEEE Fellows

Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents: Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he […]

The IEEE S3S Conference Delivered Impressive Technical Content

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]