SOI Pioneers Mazure and Raskin Join Ranks of IEEE Fellows

Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents: Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he […]

The IEEE S3S Conference Delivered Impressive Technical Content

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

Leti’s 10nm FD-SOI Models in June ’14

“French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014),” reports Chris Edwards in Tech Design Forum.

Memoir Systems’ Memory IP Now in ST’s FD-SOI ASICS & SOCs

Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs. “With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to […]

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

Rambus will have access to ST’s FD-SOI process-technology design environment

Under a new agreement, Rambus will have access to ST’s FD-SOI process-technology design environment. With this, Rambus will be able to benefit from FD-SOI’s reduced silicon geometries and lower power consumption at 28nm and below in its future memory and interface solutions. This is part of a comprehensive agreement between the two companies, which covers […]

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array […]