Silicon Europe (an alliance of Europe’s leading micro- and nanoelectronics clusters) and the SOI Consortium have organized an SOI Workshop on the 7th of July 2015, during the 10th Silicon Saxony Day in Dresden.
Here’s the agenda:
The workshop, which runs from 1:30 – 4:30, will be held in English. There is an entry fee (waived for students) for Silicon Saxony Day, but once you’re in, the SOI Workshop is free.
With five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.
Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?
Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.
Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.
ASN: When did X-Fab first start offering SOI and why?
TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.
ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?
TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.
Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.
ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?
TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.
Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.
ASN: When and why do your customers choose an SOI-based process?
TM: Typically, we see two types of SOI customers:
ASN: Can you expand on the time-to-market (TTM) issue a bit?
TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.
ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?
TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.
ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?
TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..
ASN: Can you tell us more about X-Fab’s SOI offerings?
TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)
Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.
XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.
XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.
ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?
TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.
For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.
We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.
ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?
TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.
We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.
We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.
ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?
TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.
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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.
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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge
**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.
April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.
Wow, were we precient.
Consider some of the topics we covered in that first edition, back in April of 2005:
FinFET on SOI (that was at 45nm)
NXP (then Philips) massive use of SOI for automotive chips (they were already running 3 million SOI-based transceivers a week back then)
a piece on low-power design with SOI by Jean-Luc Pelloie, who’s now an ARM Fellow and the company’s Director of SOI Technology
Intel had just published their first photonics on SOI papers in Nature (and yes, their photonics program is absolutely still on SOI)
ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.
The presentation is now posted on SlideShare (click here to see it).
It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.
If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.
We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)
Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.
Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.
And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.
In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.
So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.
The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.
I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.
In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.
With warm regards,
A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume. Olivier Thomas, who’s in charge of the program and Ali Erdengiz, who’s Business Development Manager for Leti explain how it works.
Advanced Substrate News (ASN): What exactly is Silicon Impulse? What services does it offer?
Olivier Thomas (OT): Silicon Impulse provides design services from emulation to test program development and qualification (emulation, advanced building blocks and IPs access, full control design flow, industrial MPW, packaging and board, test and qualification).
So you can consider Silicon Impulse as a silicon enablement and development platform: a unique IC prototype development and production hand-off partner for companies in need of the latest low-power semiconductor technologies and heterogeneous integration solutions (FD-SOI, BEOL NVM, MEMS, 3D…). We work with a strong network of industrial partners and offer a single entry point along product maturation.
Silicon Impulse leverages Leti’s* and List’s** expertise as well as top industrial partners belonging to a global network of experts in analog, RF, digital and memory design, as well as hardware/software-integrated solutions.
In a nutshell, Silicon Impulse offers:
[Editor’s note: Click here to download the Silicon Impulse brochure.]
ASN: Who is it aimed at?
Ali Erdengiz (AE): We saw that the increasing cost of leading semiconductor technologies, the level of expertise, tools and resources required to develop innovative products using such advanced processes can make it really challenging for new entrants (product and solution innovators). So CEA Leti created the Silicon Impulse initiative to help innovative companies to get their projects off the ground. We provide an advanced silicon development platform, help them develop their IC and/or subsystem and then hand it off to the production supply chain.
We did this because we see that today’s new markets are driven by a variety of applications and new players – it’s not just the big players scaling for PCs and mobiles anymore. IoT is a great opportunity for the emergence of innovations and ideas from new entrants. We’ve been getting more and more requests from partners looking to integrate the advanced technologies developed in Leti such as BEOL NVM and MEMS. They’re thinking outside of the box, so they are also interested in using 28nm FD-SOI while requesting advanced features and specific performance at low-voltage. Leti has always done technology research. Now with Silicon Impulse we provide a new service in collaboration with other industrial partners to help companies evaluate, design, prototype, and launch their products.
ASN: If FD-SOI design is so easy and so close to what designers have done in bulk, why do they need this sort of service?
OT: Indeed, one can easily migrate from bulk to FD-SOI and benefit immediately from its low power/low leakage characteristics. However, we’ve seen that many of the companies that port their circuits to FD-SOI don’t exploit the full potential of the technology. Silicon Impulse leverages Leti’s strong expertise and experience in FD-SOI technology from device to Digital/RF modeling and advanced design solutions and maximizes the gains of the technology. Our competence center provides its industrial partners with quick access to information, know-how and silicon proven advanced design and architecture solutions to efficiently manage performance, power consumption and process variability. Here are some examples: PVT sensors, timing fault tracking, control theory module (i.e. algorithm to figure out the optimum energy point), fast feedback loop on the top of tailored charge pump and other blocks to back bias efficiently.
In addition, Leti’s Silicon Impulse’s expertise is not limited to designing FD-SOI IC’s. Leti brings a wealth of system knowledge and application know-how from device technology through embedded software that ensures full success and differentiation for its partners’ projects.
ASN: Why should designers consider FD-SOI?
OT: The 28nm/22nm technology nodes are seen as a long-lived technology node and a sweet spot for performance, power and cost. FD-SOI is optimized for low-voltage, low-power applications that can nevertheless need high performance.
For digital design, the extended range (+/-2V) of back biasing along with PVT sensors, timing fault tracking, theory control module and fast feedback loops controlling the back bias enable efficient process compensation and energy optimization for a wide range of applications (E. Beigne et al. ISSCC’14).
For SRAM design, the un-doped planar technology offers a large portfolio of SRAM bit-cells (High-density, Low power, High-performance) enabling very good performance over a wide voltage range. The Single P-Well bit-cell architecture combined with a wide back bias range enables both low operating voltage and fast access time. In sleep mode, the back bias can be set to minimize the bit-cell standby leakage current and the data retention voltage (O. Thomas et al. IEDM’14).
For RF design, one key aspect shown in the paper presented at ISSCC 15 is the continuous re-configurability through VT adjustment by the back-gate. The Power Amplifier discussed in the paper can pass from a high-linearity/high-efficiency state to a high power state by continuous linear tuning; something that cannot be done in other technologies. At the same time, the 28 FD-SOI allows designers reach much higher FT/Fmax than bulk. The result is higher available gain in mm Wave (as shown in our example at 60GHz). This approach drastically reduces the PA’s power consumption in 90% of the use cases, thus enabling WiGig for example in mobile applications.
ASN: What are the logistics for getting started?
OT, AE: Silicon Impulse can help innovators with their projects from concept through production hand-off. To get started on a project, we do a business review to determine where and how Silicon Impulse can contribute. We can provide architectural advice and shape the product from a very high level, develop a feasibility study and make recommendations as to how to implement the system. Leti and its partners can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, MEMS, 3D components and any other advanced technology to shape a truly unique and advanced yet manufacturable product. Another layer of contribution of Leti, List would be in providing embedded software to complete the whole product. So Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between.
ASN: You’re running multi-project wafer (MPW) shuttles – can you tell us more about that?
OT: Leti offers its MPW shuttles to open the doors to a wider set of users and projects (some of whom might not have access to or be ready yet for full service foundries). An MPW shuttle serves two main purposes:
However, we’ll also be making an announcement in the near future with details of schedules for planned MPW shuttles with our industrial partners.
ASN: How long will it take to get to a working design?
AE: This is project dependent, but leveraging Leti’s experience and already proven IPs and methodologies it is likely that our partners will develop a successful design even faster than if they did it on their own regardless of whether they used FD-SOI or bulk. Using FD-SOI for digital design targeting low power without compromising performance will certainly get you there faster than using bulk. In addition, the intrinsic characteristics of FD-SOI and much better control of device variability will accelerate analog and RF design and reduce time to market.
ASN: Will the design then be transferable to a full-service, high-volume fab?
OT: The purpose of Silicon Impulse is to ease IC prototype development and enable/accelerate production ramp-up. Silicon Impulse completes the Leti R&D offering by transferring the technology into a manufacturable product. The production is then handed off to a full service fab and/or supply chain partner. We’ll begin announcing the names of these partners shortly.
For information on contacting Leti’s Silicon Impulse service, click here.
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Olivier THOMAS is the project leader of Silicon Impulse for Leti. He received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti’s advanced memory design activity. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.
Ali Erdengiz is Business Development Manager for Leti/List. He has spent 20 years in Silicon Valley and held various engineering, marketing, product and business unit management functions at companies such as ST Micro, National Semiconductor, Fujitsu, Altera, Abound Logic and eSilicon. Ali holds a BSEE from ESME, an MSEE from Université Parix XI and an MBA from San Jose State University.
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*CEA-Leti is a research-and-technology organization with a large and word class expertise from device through system integration. It specializes in nanotechnologies and their applications. NEMS and MEMS are also at the core of its activities. Leti is capable of not only developing semiconductor devices (analog, mixed-signal, RF, digital, MEMS) but also integrating them into subsystems using PCB, MCM, 2.5D and 3D technologies as well as developing embedded and application software to deliver full system level solutions.
**A sister organization to CEA-Leti, CEA-List conducts R&D in fields that create value for the economy and society. As such, the primary mission is to give businesses the tools they need to turn their innovative ideas into marketable products.
Semicon China (Shanghai, 17-21 March 2015) was an awe-inspiring event. The sheer size and the energy were dazzling. But it was the investment plans prompted by the government’s injection of RMB 120 billion (US$19.6 billion) last fall in seed money for the industry with supporting local funds pouring in that was clearly the source of a lot of adrenalin and M&A talk.
China’s industry is in high gear, still posting double-digit growth. But here’s the rub: while China consumes about half of the world’s roughly US$ $350 billion in chips (2015, WSTS), fabs in China only account for 2.5% of worldwide revenue. They’d like to see that change in a big way, and fast.
Hence Beijing’s IC Investment Fund, which is expected to continue to be expanded. SEMI estimates that the total government (central plus local) funds will reach US$100 billion, plus it’s prompting the creation and growth of additional local government and industry funds. (Dr. Adam He at SEMI has done an excellent job explaining Beijing’s investment strategy – you can see his summary here.) New VC funds are popping up everywhere, and existing ones are being augmented.
Which is why everybody was calling it the best time the industry’s ever seen. In his talk, Handel Jones of IBS, called it a once-in-a-lifetime opportunity.
This should represent significant opportunities for the SOI ecosystem in China. China foundries are offering RF-SOI already (click here to read about the Shanghai RF-SOI Workshop). And it is worth noting that China’s R&D institutes have deep expertise in all things SOI.
FD-SOI is an important topic (click here to see an ASN piece on FD-SOI by a professor at a top Beijing institute from last year, and here for more about the recent Shanghai FD-SOI workshop). China’s designers are hot on FD-SOI, too. (Did you hear about how the Beijing cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015? Read about it here.)
SOI-based MEMS, power, and sensors products are also already produced in China’s foundries. In fact SOI was a strategic focus by key institutes like SIMIT under the national “Innovation 2020” 5-year plan launched in 2010.
In terms of SOI wafers, China’s wafer leader, Simgui also works closely with Soitec, the world’s SOI wafer leader. Not surprisingly, theirs was a busy stand at Semicon China.
The Hot Topic: M&A
During the keynotes and industry sessions, M&A were central themes, as China looks beyond its borders for expertise. Hardly a talk went by that didn’t touch on this topic, all emphasizing that 1 + 1 > 2, and hammering home the importance of holding on to top talent in takeover scenarios. With each new slide, a sea of smartphones raised above the crowd to capture the onscreen tips.
In fact, with the IC Investment Fund taking center stage, the head of China Merger & Acquisition at Goldman Sachs gave the audience a primer on the M&A process. China, he noted, is now number two for M&A worldwide, just behind the US. While in the past the activity was “inbound”, China’s companies are now active on a transnational scale. This year will be an M&A record breaker for the semiconductor industry in China.
China’s expats are returning in droves from abroad, founding new companies. New industrial parks like the one out by the Shanghai airport are attracting major investors.
Big Show, Small World
This was the biggest Semicon ever, with 2750 booths covering 57,000m2 (over 600,000 sq. ft – more than three times the size of West) and over 50,000 visitors (almost twice what they got at West+Intersolar last year).
But Semicon China also had its small-world moments that show just how far SOI is reaching. Consider this. I was on the metro in Shanghai, heading over to Semicon, reading the show program. The guy next to me asked a question about the show (he was heading there, too), and we got to chatting.
It turns out he’s the founder of Trinamic, a German company that designs chips for motion control. They have just started an SOI project with X-fab as the foundry. He’s very clear and enthusiastic about what he expects SOI to do for them. It’s for a high-volume app in small, precision motor control for things like video surveillance cameras.
This is an encouraging indication of just how far the SOI ecosystem is reaching! (We have an interview coming up with the folks at X-fab, btw, so keep an eye out for that.)
We’ll also have lots more from China, including interviews and profiles of the institutes and companies that are major players in the SOI ecosystem there. It’s truly an incredible place to be right now.
The Heterogeneous Technology Alliance (HTA), a coalition of top European R&D organizations, is offering an SOI-MEMS platform. Looking to bridge the gap between academia and industry, this technological platform pools the SOI-MEMS expertise, capabilities and fabrication facilities of Leti (France), Fraunhofer (Germany), CSEM (Switzerland) and VTT (Finland).
The main focus of HTA (click here for the website) is the further development of innovative Smart Systems. SOI-MEMS is typically used for silicon oscillators, microphones, speakers, compass, navigation, motion sensors, sensors and actuators, energy harvesting, micro fuel cells, microfluidics and other deep reactive-ion etched micro structures. A recently issued brochure gives an overview of the offering.
The HTA is active at all levels of Smart Integrated Systems Solutions: from applied research on materials, processes and equipment through the fabrication of devices and components to the development of new products and services. Development and small-scale production cleanrooms for micro-electronics, MEMS, power electronics and analogue components is available. Wafer handling capacity encompasses wafer sizes ranging from 100, through 150 and 200 to 300 mm.
A one-stop shop for complete system solutions, the HTA guarantees simple access to an enlarged portfolio of technologies and is structured to facilitate technology transfer to European and non-European companies. In addition to working with large industrial partners, the HTA offers services specially suited for small and medium-sized companies. With a combined staff of more than 5,000 scientists and a portfolio of more than 3,000 patents, the HTA is de facto the largest European organization in the field.
SiTime’s SOI-MEMS solution is a key part of a new realtime health and fitness tracking solution from MegaChips called “frizz”. MegaChips has announced a partnership with Bosch Sensortec to provide a complete reference design for use of frizz in smartphones, wearables and other personal devices allowing consumers to monitor their activities in real time (read the press release here).
This marks SiTime’s first major announcement since becoming a subsidiary of Mega chips. SiTime leverages SOI-MEMS for high-performance, ultra-low power, ultra-slim timing solutions. (SiTime contributed an excellent piece to ASN a few years ago explaining their SOI edge – you can still read it here.)
Piyush Sevalia, SiTime marketing EVP, said, “SiTime’s groundbreaking MEMS and programmable analog technologies allow us to deliver game-changing MEMS timing solutions. Our MHz and kHz solutions provide the best accuracy, the smallest size and the lowest power, all of which are ideally suited for wearable electronics and internet of things (IoT).”
Frizz is a motion sensor hub with a 32bit DSP based motion engine that can realize high performance calculations used in processing algorithms with ultra-low power consumption in lieu of a microprocessor. MegaChips’ ultra-low power frizz, combined with the SiTime SiT1602 programmable MHz oscillator and Bosch Sensortec MEMS sensors provide more meaningful data, easy interpretation, higher accuracy and ultra-low power critical for longer battery life.
The joint frizz and Bosch Sensortec solution is available now from MegaChips (extensive information is available here).
Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies used for R&D and manufacturing of semiconductors, LEDs, MEMS and photovoltaic devices.
The company’s newest inspection system, the Orion Lightspeed™, is capable of pinpointing the size and location of nano-scale defects inside compound semiconductor materials and transparent substrates (see press release here). The new system helps to ensure the quality control of high-value engineered substrates used in several fast growing markets including high-brightness LEDs, power semiconductors and 3D ICs. Inspection is based on Altatech’s patented synchronous Doppler detection™ technology, which determines the exact size and position of defects by making direct physical measurements with resolution below 100 nm. This provides true defect sizing, as opposed to other types of inspection equipment on the market that make indirect measurements using diffracted light to calculate approximate defect sizes. It handles 200mm or 300mm substrates, with throughput of 85 and 80 wafers per hour, respectively. Beta systems have already been installed at customers’ facilities and are demonstrating excellent performance. Shipments of production units are scheduled to begin in April 2015.
The new AltaCVD 3D Memory Cell™ is the latest member of Altatech’s AltaCVD line, designed to deposit ultra-thin semiconductor films that enable the manufacturing of high-density, low-power memory ICs used throughout mobile electronics (see press release here). The new system performs atomic-layer deposition 10 times faster than conventional atomic-layer deposition (ALD) systems, helping to meet global market demands for both high-volume production and cost efficiency in fabricating advanced memories. The system is currently demonstrating its unique capabilities and performance at one of Altatech’s key customers. Production units are available.