NXP crossover processor on FD-SOI will be even more spectacular (EETimes)
When the next generation of NXP’s ground-breaking “crossover processors” come out in 2018, they “…will use a fabric of i.MX 7 and 8 processors manufactured by using a 28-nm FDSOI process,” and they “…will be more spectacular and complex.” That’s what NXP’s senior vice president and general manager of microcontrollers Geoff Lees recently told EETimes International Correspondent, Junko Yoshida (see the full article here).
NXP announced the i.MX RT series during ARM Techcon (see press release here). Essentially they represent a convergence between application processors and MCUs. With the high performance and functional capabilities of applications processors, but with the ease-of-use and real-time deterministic operation of traditional MCUs, NXP sees applications in audio subsystems, consumer and healthcare, home and building automation, industrial computing, motor control and power conversion.
China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Sciences in Shanghai giving a keynote address at the 5th Shanghai FD-SOI Forum. (Photo courtesy: Simgui and the SOI Consortium)
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
- 5th Shanghai FD-SOI Forum
- 2017 International RF-SOI Workshop (Shanghai)
- FD-SOI Design Tutorial (Shanghai)
- 2017 SOI Consortium Summit Forum and Tutorial (Nanjing)
(Photo credit: Adele Hars)
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
RF-SOI coverage included pieces in leading publications such as China IC, EETimes China, EDN China, EEFocus and SemiInsights.
ARM Steps Up! And More Good News From Consortium’s FD-SOI Symposium in Silicon Valley
ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.
The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.
Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.
ARM Pitches In
If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.
CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.
FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF. ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).
ARM worked with Samsung to compare libraries on 28nm bulk vs 28nm FD-SOI, and came back with these very impressive results. (Courtesy: ARM, SOI Consortium)
The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption. Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.
In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.
NXP – New Levels in ULP
Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)
NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing. A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP) is heading to new levels, he says.
With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.
Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)
Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.
And Much More
Briefly, here are some more highlights.
Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings. But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.
Dreamchip: Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection. They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB). The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.
Dreamchip is using Arteris IP for their ADAS chip in GF’s 22nm FD-SOI (Courtesy: Dreamchip, SOI Consortium)
Greenwaves: CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros. The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.
Greenwaves expects big power savings in their move to FD-SOI. (Courtesy: Greenwaves, SOI Consortium)
Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.
IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim. FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.
The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp. IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled: lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.
All in all, it was another really good day for FD-SOI in Silicon Valley.
Must Read! EETimes Covers NXP’s First FD-SOI Chips and FD-SOI Symposium
EETimes Editor Rick Merritt has posted an excellent piece entitled NXP Shows First FD-SOI Chips. He attended the SOI Consortium’s recent FD-SOI Symposium in Silicon Valley, and used the event to score interviews with key executives from NXP, Samsung and GlobalFoundries. The piece has generated a big buzz, having been shared several hundred times on LinkedIn and retweeted extensively on Twitter.
NXP’s new i.MX 7ULP On 28nm FD-SOI – Yes! Industry’s Lowest Power General Purpose Applications Processor (part 1)
They’re calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It’s NXP’s new i.MX 7ULP general-purpose processor, and it’s on 28nm FD-SOI. They’ve got a nifty video summing it all up – you can watch it here.
NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It’s got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)
With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.
The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.
Hello, IoT!
The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.
With the i.MX 7ULP, NXP’s targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it’s designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)
The details
The i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It’s got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors.
(Courtesy: NXP)
NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.
Leveraging body biasing and more
NXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.
In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages:
-
Large dynamic gate and body biasing voltage range
-
Domain and subsystem optimization with custom standard cell library with mixed voltages
-
Low quiescent current (Iq) bias generators
-
Enhanced ADC performance with unique FD-SOI attributes
-
Fail Safe I/O for simplified low power system design
To that, add a note about security. As the chip’s fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it’s needed.
Samsung fabs, Verisilicon adds IP
Two other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP’s results.
“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”
NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.
“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”
So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.
— By Adele Hars, ASN Editor-in-Chief
Part 2: NXP’s new i.MX 7ULP – More on Why It’s On 28nm FD-SOI
i.MX 7ULP (Courtesy: NXP)
As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.
If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)
To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:
-
Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.
-
Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.
-
Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.
-
Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.
-
Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.
-
RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.
-
Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.
-
Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.
-
Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.
But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”
Next up: i.MX 8 for automotive +
At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.
We’ll cover it in an upcoming ASN blog, so stay tuned!
— By Adele Hars, ASN Editor-in-Chief
NXP, Qualcomm, Skyworks to Keynote IoT Theme in Upcoming IEEE SOI-3D-SubVt (S3S) Conference (San Francisco, Oct.’16) – Late News Submissions Open, Advance Program Available
IEEE S3S Conference
10-13 October 2016
Hyatt Regency San Francisco Airport
IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference
Theme: Energy Efficient Technology for the Internet of Things
Late News submissions open and Advance Program available
The IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.
This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.
We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.
Our Keynote speakers are decision-makers from major industries:
- Nick Yu, VP, Qualcomm, will explain why “The Homogeneous architecture is a dead fairy tale”
- Ron Martino, VP, NXP, will present “Advanced Innovation and Requirements for future Smart, Secure and Connected Applications”
- Peter Gammel, CTO, Skyworks, will describe “RF front end requirements and roadmaps for the IoT”
Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.
Applications will be illustrated in our session dedicated to SOI circuit implementations.
You can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.
And you still have time to actively participate by submitting a late news paper before August 31st.
The conference has a long tradition of allying technical and social activities.
This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.
Hyatt Regency San Francisco Airport
With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.
Deadline for Late News submissions is
August 31st, 2016
For further information, please visit our website at s3sconference.org or contact the conference manager:
Joyce Lloyd • 6930 De Celis Pl., #36
Van Nuys, CA 91406
T 818.795.3768 • F 818.855.8392 • E manager@s3sconference.org
FD-SOI at DAC 2016
If you’re headed to DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick rundown.
Synopsys-GlobalFoundries: Dinner!
Synopsys (stands 149 & 361) and GlobalFoundries are hosting a dinner on Tuesday evening (7 June) at the Austin Hilton around the theme, What’s Important for IoT—Power, Performance or Integration… or All of the Above? They’ll be talking about how FD-SOI addresses these challenges. Panel members will discuss design techniques to push the envelope on low power, low leakage, burst performance and optimal cost to enable the design of innovative IoT-based products. Attendance is free, but registration is required and seating is limited. Click here to go to the registration site.
Samsung Foundry – Showcasing 28FDS
Samsung Foundry (stands 607 and 706) and partners will be doing a number of presentations on Samsung’s 28nm FD-SOI offering, 28FDS. They’ll be showcasing 28FDS wafers, offering multiple presentations by Samsung Foundry’s experts, and sharing solutions built on the 28FDS technology by their Foundry Ecosystem partners. As noted in ASN coverage of the recent SOI Consortium event in San Jose (read it here), Samsung is now in commercial production of 28FDS. They have a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast.
Panels & Presentations
IP Track: Minimizing SOC Power Consumption: A Top Down Design Methodology or Bottoms Up Starting With the Process Selection Problem? Panelists include Carlos Mazure (of the SOI Industry Consortium & Soitec) and Ron Martino (of NXP) Monday, June 6th from 4:00pm – 5:00pm in Ballroom G.
Variation-Aware Design at Advanced and Low-Power Processes. Panelists include Azeez Bhavnagarwala (ARM), Glen Wiedemeier (IBM), John Barth (Invecas) and Jeff Dyck (Solido). Monday, June 6th from 10:30am – 11:30am, Room: 9BC.
Presentation 9.1 Impact of Leakage & biasing on Power in 22FDX Process. By Krishnan Subramanian et al (Invecas) and Sankar Ramachandran – (Apache Design). Monday, June 6th, 3:30pm – 4:00pm, Ballroom G.
Presentation 50.4 Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search. By Johannes M. Kuehn et al (Eberhard Karls Univ. Tubingen & Keio Univ.) Wednesday, June 8th, 1:30pm – 3:00pm, Room: 17AB. This presentation will be given at 2:15. (You can also get the paper from the ACM site here.)
101.12 Parametric Exploration for Energy Management Strategy Choice in 28nm UTBB FDSOI Technology. By Jorge Rodas et al (CEA-Leti Minatec & Univ. Grenoble Alpes) Work-in-Progress (WIP) poster session, Wednesday, June 8th, 6:00pm – 7:00pm, Room: Trinity St. Foyer
Stands & More
Cadence Theater (stand 43 – full schedule here)
Tuesday, June 7th
- 1:00pm – Opening a New Dimension in Design with GlobalFoundries 22FDX Technology (presented by GlobalFoundries)
- 5:00pm – Ultra-Low Voltage SRAM: Addressing the Characterization Challenge (presented by SureCore – see their recent ASN piece here)
- 5:30pm – Announcing Global MEMS Design Contest (presented by X-Fab – so not FD-SOI, of course, but they’ve got leading-edge, SOI-based solutions for MEMS, analog/mixed-signal and more. Read the interview in ASN here)
Wednesday, June 8th
- 3:00pm – Analog and Mixed-Signal Design with GlobalFoundries 22FDX Technology (presented by GlobalFoundries)
Leti (stand 1818) – a driving force behind all things SOI, stop by to learn more about Silicon Impulse®, their FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume (more here).
CMP (stand 343) – they’ve been delivering multi-project wafer runs of 28nm FD-SOI for a few years now (as seen in ASN here).
And finally, the opening keynote on Monday morning (at 9:15 in Ballroom A) will be given by NXP’s Lars Reger, CTO of their Automotive Business Unit. The topic is Revolution Ahead – What It Takes to Enable Securely Connected, Self-Driving Cars. When it comes to automotive, NXP is the original SOI pioneer, dating to back to 1999. NXP’s sold billions of SOI-based chips for high-voltage automotive applications – they’re used by virtually every carmaker on the planet (read about the early history here and here).
And now with the Freescale acquisition, NXP is full speed ahead with FD-SOI applications processors. If you missed it, you’ve got to read the recent ASN series by Ron Martino (NXP’s VP for i.MX Applications Processor and Advanced Technology Adoption). He explains why they chose 28nm FD-SOI, and exactly what it does for the i.MX 7 series (32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets) and i.MX 8 series (64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications) Click here to read it now. NXP gave a demo of the I.MX 8 at FTF 2016 a few weeks ago – check out the video they posted on Twitter here.
If you go to DAC and you have a Twitter account, be sure to tweet #FDSOI and #53rdDAC – @followASN will be happy to pass it along!
San Jose Symposium: It Was an Epic Day for FD-SOI – Now Dubbed “The Smart Path to Success” [Part 1 of 2]
The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.
So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!
Samsung – in 28FDS mass production
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:
Samsung’s foundry began commercial production of 28nm FD-SOI in 1Q2016.
At the San Jose symposium, ST showed once again the enormous advantages FD-SOI provides in analog design.
As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).
NXP – integration, differentiation and passion
Ron Martino gave a talk full of energy and passion entitled, “Smart Technology Choices and Leadership Application Processors,” (which you can download from the SOI Consortium website – click here).
If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.
As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.
In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:
(Courtesy: NXP and SOI Consortium)
For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”
Sony – GPS (with 1/10th the power!) now sampling
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).
In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.
As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.
Analog Bits – Lowest Power SERDES IP
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.
With the port to 28nm FD-SOI, Analog Bits now has the industry’s lowest power SERDES.
In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”
Stanford – FD-SOI for the Fog
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.
So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
~ ~ ~
*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
Why NXP’s i.MX 7 and 8 Applications Processors are Taking on IoT, Wearables, Automotive and Other Embedded Markets with 28nm FD-SOI [Part 2 of 2]
By Ronald M. Martino, Vice President, i.MX Applications Processor and Advanced Technology Adoption, NXP Semiconductors
At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI.
As noted in part 1 of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable and IoT markets, where power efficiency is paramount. The i.MX 8 series leverages the 64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, and well as high-performance general embedded and advanced graphics applications.
Choosing an FD-SOI solution gave our designers some specific tools that helped them to more easily and robustly deliver the features our customers are looking for. Here in part 2, we’ll look a little more deeply into the markets each of these chip families is targeting, and the role FD-SOI plays in helping us meet our specs.
i.MX 7 Series: IoT, wearables and so much more
Announced last June, the first members of our new 7 series — the i.MX 7Solo and i.MX 7Dual product families — will be hitting the market shortly. We’ve been shipping samples since last year, and the response has been tremendous. (You can read about the i.MX 7 IoT ecosystem we’re helping create for our customers here and support for wearable markets here.)
Our i.MX 7 customers are building products for power- and cost-sensitive markets. That of course includes a vast array of innovative IoT solutions and wearables, but also solutions for other parts of the embedded market like handheld point-of-sale (POS) and medical devices, smart home controls and industrial products. The i.MX 7 series also continues NXP’s industry leading support for the e-reader market via integration of an advanced, fourth-generation EPD controller.
For all these markets, excellent performance is very important, but both dynamic and static power figures are really key. When you’re creating a system with power efficient processing and low-power deep sleep modes, you enable a new tier of performance-on-demand, battery-operated devices that are lighter and cheaper, and in a virtuous cycle require smaller batteries.
The next members of the NXP i.MX 7 series combine ultra-low power (dynamically leveraging the reverse back biasing you can do with FD-SOI) and performance-on-demand architecture (boosted when needed with FD-SOI’s forward back-biasing). It’s the industry’s first general purpose microprocessor family to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (customers can choose between single or dual A7 cores). These technologies, together with our new companion PF3000 power management IC, unleash the potential for dramatically innovative, secure and power efficient end-products for wearable computing and IoT applications.
The initial offering of i.MX 7 was designed (on 28nm bulk) with Cortex-A7 cores operating up to 1 GHz, while the Cortex-M4 core operates at up to 200 MHz. The Cortex-A7 and Cortex-M4 achieve processor core efficiency levels of 100 microWatts (μW) /MHz and 70 μW /MHz respectively.
A Low Power State Retention (LPSR), battery-saving mode can be improved by FD-SOI and consumes only 250 μW, representing a 3x improvement over our previous generation (on 40nm bulk). That’s almost 50% better than our competitors. Plus it minimizes wake up times without requiring Linux reboot, while supporting DDR self-refresh mode, GPIO wakeup, and memory state retention.
The next members of the i.MX 7 series, with FD-SOI dynamic back-biasing, enable different blocks to be reverse or forward back-biased on the fly to attain always-optimal power savings or performance. Additional power optimization features are enabled to achieve leadership power efficiency. We’ve optimized FD-SOI dynamic back-biasing to enable performance-on-demand architecture through which the i.MX 7 series meets the bursty, high-performance needs (this is when forward back-biasing kicks in) of running Linux, graphical user interfaces, high-security technologies like Elliptic Curve Cryptography, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.
When high levels of processing are not needed, low-power modes kick in with reverse back biasing of the critical subsystems, and the ongoing, real-time work is carried on by the smaller, lower powered Cortex-M4.
All things considered, it’s perhaps no surprise that we expect i.MX 7 series solutions for cost-sensitive markets to be a key driver of our long-term i.MX portfolio expansion.
i.MX 8: Revolutionizing automotive, interactive multimedia/display apps
Our new i.MX 8 series portfolio, based on 28nm FD-SOI process technology, targets highly-advanced driver information systems and other multi-media intensive embedded applications. It incorporates those same key attributes as the i.MX 7, but extends them into realms the industry has never experienced. We believe the i.MX 8 series is poised to revolutionize interactivity in multimedia and display applications across all kinds of industries.
i.MX 8 incorporates innovations in the processor — complex graphics, vision, virtualization and safety to help revolutionize interactivity for a wide range of uses in many, many markets. The capabilities of this family is broad, but one of the places it’s going to be the biggest game-changer is in what is becoming the e-cockpit of your car.
For almost two decades, SOI has shone in the embedded processing world. In addition, NXP counts every major automotive maker in the world amongst its customers for our devices. Entering the new e-cockpit frontier, 28nm FD-SOI is the logical choice in making the i.MX 8 series meet and exceed the stringent requirements of top automotive OEMs for years to come.
The i.MX 8 series leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s. All the FD-SOI advantages discussed above for the i.MX 7 are also being brought to bear here (the power envelope for automotive designers being extremely strict). But in the hot and electrically noisy automotive environment, FD-SOI also plays an important role in ensuring robust operation.
The way we see it, your car’s multimedia centric e-cockpit will revolve around the i.MX 8, a single chip that drives all displays from infotainment to heads-up-displays (HUD) to instrument clusters. It’s optimized for the intelligent transfer of data and information management from multiple subsystems within the IC – as opposed to only delivering raw performance through one or two processing blocks.
For drivers and passengers alike, we’re looking at a very different world: one that includes the spread of advanced heads-up displays, intuitive gesture control, natural speech recognition, augmented reality, enhanced convenience and device connectivity. (I wrote a blog exploring the possibilities last fall – you can read it here.)
And of course, it will be secure from hackers, and fail-safe for critical systems.
From our customers’ standpoint, they can design a single hardware platform and scale it across multiple market segments with the unique approach to pin and software compatibility within the i.MX product families.
The i.MX family has been leveraged in over 35 million vehicles since it was first launched in vehicles in 2010. So with all these new features, and low-power and robust performance, we see a very bright future for FD-SOI and the i.MX 8 in automotive. It’s going to be a great ride.