Tag Archive Photonics

ByGianni PRATA

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS’ customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology. Co-founded by Leti and imec in 2009, ePIXfab offers a cost-effective way for researchers and small and medium sized companies to prototype photonic integrated circuits on SOI.

ByAdministrator

Common Platform Technology Forum 2013: SOI Highlights

The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here to register and watch it yourself).

The Common Platform Alliance is IBM, Samsung and GlobalFoundries, operating, as IBM’s Dr. Gary Patton points out, as a “virtual IDM”.

Here’s a round-up of the SOI-based highlights.

Dr. Gary Patton, Vice President of Semiconductor Research & Development Center, IBM

In his keynote address, Gary covered the following SOI-based innovations:

  • FinFETs: As ASN readers know, IBM is driving FinFETs very hard. With ARM & Cadence, they taped out their first 14nm FinFET processor last fall (on SOI). Gary’s talk gave an overview of the evolution of device structures, including PD-SOI (the basis for IBM’s Watson supercomputer), FD-SOI, FinFETs and future structures and materials.
  • Wearable electronics & folding displays – IBM has developed a new, low-cost technique that starts with the FD-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. Gary showed a sample, and said that “research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.”
  • Carbon nanotubes breakthrough – IBM has attained 10,000 working nanotube transistors on a single device using standard semiconductor processes.  As we noted in ASN when this news broke last fall, IBM researchers fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat rows rather than a spaghetti-like tangle.
  • Silicon nanophotonics – most all of the industry’s nanophotonics work is on SOI, and IBM is no exception here.  As Gary notes, “…the key innovation isn’t just the technology…it’s the fact that it’s commercial and scalable…”.
Everywhere computing

Flexible computing with FD-SOI. (Courtesy: IBM, Common Platform Technology Forum 2013)

IBM Carbon Nanotubes SOI

As seen here, carbon nanotubes start on an SOI wafer. (Courtesy:IBM, Common Platform Technology Platform 2013)


Mike Noonen, Executive VP, Global Sales, Marketing, Quality & Design, GlobalFoundries.

In Mike’s keynote on particularly innovative customers, he covered ST’s FD-SOI technology.  Here are the main points he made about it:

  • STMicroelectronics has been a partner in the Common Platform.
  • FD-SOI leverages 80% FEOL of the 28nm SLP; the BEOL is identical to 28nm LP.
  • “You can really dial-in optimal transistor performance,” he said.  The thin silicon channel introduces “interesting and exciting capabilities”, including:
    – lower leakage, lower capacitance, enhanced latch-up immunity, electrostatic control;
    – speed boost through back biasing;
  • This technology is a simpler planar process:
    – reduced masks offsets cost;
    – considerable IP reuse.
  • With a nod to Soitec, the world-leader in SOI wafers, he said, “Soitec has been a really enthusiastic evangelist of this technology, and I really want to acknowledge their efforts in making Fully-Depleted over SOI something that the industry has become very excited about.”  He added that they’re joined by MEMC and SEH as SOI substrate suppliers.
  • Regarding the roll-out, he concluded, “A PDK of this technology is available this quarter, and GlobalFoundries has partnered with ST for volume manufacturing and will be entering risk production in the 4th quarter of 2013, with volume production in the first half of 2014.”
GlobalFoundries ST FDSOI

GlobalFoundries’ keynote highlights FD-SOI. (Courtesy: GlobalFoundries, STMicroelectronics, Common Platform Technology Forum 2013)

Handel Jones, Owner & CEO, International Business Strategies

In a “fireside chat” with Brian Fuller, Silicon Valley Bureau Chief, EETimes, Handel Jones touched on a number of SOI-related topics.  (In case you missed it, Handel recently wrote an excellent article for ASN on FD-SOI vs. Bulk & FinFET economics.) In addition to his general discourse on the impact of design & process issues on cost/gate, the importance of the ecosystem, and general industry outlook, here are some of Handel’s SOI-related observations during the forum chat:

  • RF: he is particularly impressed with IBM’s work on RF, which he says is “…doing extremely well.”  As you may have seen previously in ASN, IBM’s CMOS 7RF SOI technology, which the company says offers significant cost advantages to designers of mobile handsets, has been on SOI for over five years.
  • FD-SOI:  When asked about any single, major disruption on the horizon, he noted that designing with FinFETs for mixed signal is tough, so there may be a delay there.  However, FD-SOI looks very positive, he says. He sees FD-SOI offering lower power, lower cost/gate, re-usable IP and scalability to 14nm.
ByAdministrator

Wafer Leaders Extend Basis for Global SOI Supply

Soitec Shin-Etsu

It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”

Soitec SOI wafers

Beyond logic

The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

Soitec Smart Cut

This illustration shows how Smart Cut, Soitec’s proprietary engineered wafer technology, works. The industry standard, this revolutionary wafer bonding and layer splitting processes makes it possible to transfer a thin layer of material from a donor substrate to another substrate, overcoming physical limitations and changing the face of the substrate industry. The Smart Cut technology was originally developed by the CEA-Leti. Soitec holds exclusive exploitation of CEA-Leti rights into the Smart Cut technology, including the right to sublicense to SEH. The technology was made viable for SOI high-volume commercial production by Soitec, and is now protected by more than 3,000 patents owned or controlled by Soitec.

ByGianni PRATA

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

Meritage Resort and Spa in Napa Valley

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)

The papers

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. FullyDepleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: FullyDepleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

The courses & panel

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

ByGianni PRATA

Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment

Imec Genalyte SOI wafer

SOI wafer with photonics biosensorchips. (Courtesy: imec)

Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte‘s diagnostic and molecular detection equipment. Founded by SOI-photonics innovator Dr. Cary Gunn, Genalyte chips contain ring resonator sensors for very sensitive molecular detection; on-chip grating couples infrared light to diagnostic equipment.

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Photonics on the Move

SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends.

The existence of Silicon Photonics owes much to serendipity. During the early years of the development of SOI wafer technology probably nobody anticipated that SOI would be a perfect medium for short distance transmission and modulation of light beams. Only in 1986 Richard Soref pointed out that SOI structure had the right properties for light confinement in near infrared1, and some years later Si waveguides started being designed.

A very large refractive index contrast between the Si and the SiO2 means that the light is very well confined inside the Si waveguide core, which can have sharp bends. This leads to very compact photonic integrated circuits (PICs) with densely spaced micron-scale photonic devices.

Silicon Photonics emerges

By coupling optical fibers with Si waveguides etched in SOI substrates, the light that is going into or coming out of such fibers can be processed.

In recent years the photonics community has developed all the devices needed for such processing, from light modulators and wavelength filters built in SOI to photodetectors made in germanium that was selectively grown on Si, all capable of handling data streams with a bandwidth of at least 10 Gb/s and often much higher.

Even the light sources, one missing component in the SOI device chain, are coming closer to Si.

Just as multiple wavelengths can propagate in a fiber (wavelength division multiplexing or WDM), they can also propagate together in a Si waveguide, and devices to multiplex and demultiplex these data streams can also be built in SOI.

Power reduction is the key

We can expect that the future silicon PICs will be built with higher complexity and reduced cost, and with reduced power/bit of data. Fully integrated silicon photonics technology for transceivers used in short (10 – 100 m) and medium (1 km) range optical interconnects in data centers and supercomputers exists now at a few companies.

The enormous bandwidth requirements and power dissipation constraints in large IT systems will advance Si photonics for inter-board and inter-chip communication, and eventually for intra-chip links.

Communication Technology Roadmap and future developments

The MIT Microphotonics Center and about 20 industrial partners released Communication Technology Roadmaps in 2005 and 2009 that address the challenges of high bandwidth communication at the lowest possible power.

At the latest Microphotonics Center Spring Meeting in April 2011, presentations covered a broad range of topics. The audience heard a provocative statement by a speaker from Alcatel-Lucent that integrated photonic circuits are unlikely to succeed since photonics devices do not scale as their size is defined by the wavelength of light. Others agreed that this indeed is the reason to aim for hybrid electronic/photonic integration since different device scales are less conducive to monolithic integration.

Speakers from NTT and AIST in Japan, Kotura, Analog Devices, and even Alcatel-Lucent presented new designs for fully integrated photonic circuits on SOI platforms.

Si PIC development will accelerate when a new photonic foundry, OpSIS (Optoelectronic System Integration in Silicon), for multi-user wafers comes on line. It is being organized by the University of Washington, with the financial backing of US government agencies and industry. BAE will be the first fab qualified to process the photonic chips for OpSiS, while two more facilities may join later.

All these developments lend credence to the emergence of silicon (in an SOI structure) as an important photonic material. Dr. Soref’s observation of 25 years ago is paying off.

 

1 R.A. Soref, J. P, Lorenzo, “All-Silicon Active and Passive Guided-Wave Components for wavelength=1.3 and 1.6μm”, IEEE J. Quantum Electron. Vol. QE-22, 873 (1986).

ByGianni PRATA

Luxtera’s new optical engine chip-set for the HPC and data center markets uses mainstream SOI-CMOS photonics fabrication processes

Luxtera’s new optical engine chip-set for the HPC and data center markets uses mainstream SOI-CMOS photonics fabrication processes (foundry: Freescale). It delivers on-chip waveguide level modulation and photo-detection, along with associated electronics, and supports four fully-integrated 14 Gbps opto-electronic transceiver channels on a single CMOS chip.

ByGianni PRATA

U.Washington is hosting a new SOI-based photonics foundry service called OpSIS

With backing from Intel, U.Washington is hosting a new SOI-based photonics foundry service called OpSIS. Looking to launch a photonics revolution as MOSIS did for electronics a few decades ago, OpSIS is a multi-project wafer service. Actual foundry services are provided by BAE Systems. Read the Intel blog entry by Dr. Mario J. Paniccia, director of the company’s Photonics Technology Lab, for his take on just how important this project is.

ByGianni PRATA

SOI-based news from IBM

SOI-based news from IBM (which has now shipped more than 100 million SOI chips):
Cu-32 Custom Logic dramatically increases memory capacity and processing speeds of chips used in fiber-optic and wireless networks, and in such gear as routers and switches.
CMOS-7HV process technology for powermanagement semiconductors targets manufacturers in consumer electronics, industrial, automotive, digital media and alternative-energy. It can lower costs and integrate the functionality of 3 or 4 chips into just one.
• Heralded as an enabler for future exascale processors, a patented new chip technology called CMOS Integrated Silicon Nanophotonics integrates transistors and nanophotonic devices in the same silicon layer, improving integration density over 10X.

ByGianni PRATA

Intel has developed a research prototype of a silicon-based optical data connection

Courtesy: Intel

Intel has developed a research prototype of a silicon-based optical data connection with integrated lasers. Integrated on SOI, the link can move up to 50 gigabits of data per second.