Tag Archive sensors

ASN Celebrates a Decade of SOI News, Views and Commentary

April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.

Wow, were we precient.

Consider some of the topics we covered in that first edition, back in April of 2005:ASN10

Not bad!

ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.

The presentation is now posted on SlideShare (click here to see it).

It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.

If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.

We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)

Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.

Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.

And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.

In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.

So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.

The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.

I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.

In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.

With warm regards,

– Adele

Huge Success of Semicon China: Opportunities in a Fast-Changing Landscape

SemiconBannerlores

Semicon China (Shanghai, 17-21 March 2015) was an awe-inspiring event.   The sheer size and the energy were dazzling. But it was the investment plans prompted by the government’s injection of RMB 120 billion (US$19.6 billion) last fall in seed money for the industry with supporting local funds pouring in that was clearly the source of a lot of adrenalin and M&A talk.

 

China’s industry is in high gear, still posting double-digit growth. But here’s the rub: while China consumes about half of the world’s roughly US$ $350 billion in chips (2015, WSTS), fabs in China only account for 2.5% of worldwide revenue. They’d like to see that change in a big way, and fast.

 

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

Hence Beijing’s IC Investment Fund, which is expected to continue to be expanded. SEMI estimates that the total government (central plus local) funds will reach US$100 billion, plus it’s prompting the creation and growth of additional local government and industry funds. (Dr. Adam He at SEMI has done an excellent job explaining Beijing’s investment strategy – you can see his summary here.) New VC funds are popping up everywhere, and existing ones are being augmented.

 

Which is why everybody was calling it the best time the industry’s ever seen. In his talk, Handel Jones of IBS, called it a once-in-a-lifetime opportunity.

 

This should represent significant opportunities for the SOI ecosystem in China. China foundries are offering RF-SOI already (click here to read about the Shanghai RF-SOI Workshop). And it is worth noting that China’s R&D institutes have deep expertise in all things SOI.

 

FD-SOI is an important topic (click here to see an ASN piece on FD-SOI by a professor at a top Beijing institute from last year, and here for more about the recent Shanghai FD-SOI workshop). China’s designers are hot on FD-SOI, too. (Did you hear about how the Beijing cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015? Read about it here.)

 

SOI-based MEMS, power, and sensors products are also already produced in China’s foundries. In fact SOI was a strategic focus by key institutes like SIMIT under the national “Innovation 2020” 5-year plan launched in 2010.

 

In terms of SOI wafers, China’s wafer leader, Simgui also works closely with Soitec, the world’s SOI wafer leader. Not surprisingly, theirs was a busy stand at Semicon China.

 

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

 

The Hot Topic: M&A

 

During the keynotes and industry sessions, M&A were central themes, as China looks beyond its borders for expertise. Hardly a talk went by that didn’t touch on this topic, all emphasizing that 1 + 1 > 2, and hammering home the importance of holding on to top talent in takeover scenarios. With each new slide, a sea of smartphones raised above the crowd to capture the onscreen tips.

 

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

 

In fact, with the IC Investment Fund taking center stage, the head of China Merger & Acquisition at Goldman Sachs gave the audience a primer on the M&A process. China, he noted, is now number two for M&A worldwide, just behind the US. While in the past the activity was “inbound”, China’s companies are now active on a transnational scale. This year will be an M&A record breaker for the semiconductor industry in China.

 

China’s expats are returning in droves from abroad, founding new companies. New industrial parks like the one out by the Shanghai airport are attracting major investors.

 

 

 

Big Show, Small World

 

This was the biggest Semicon ever, with 2750 booths covering 57,000m2 (over 600,000 sq. ft – more than three times the size of West) and over 50,000 visitors (almost twice what they got at West+Intersolar last year).

 

But Semicon China also had its small-world moments that show just how far SOI is reaching. Consider this. I was on the metro in Shanghai, heading over to Semicon, reading the show program. The guy next to me asked a question about the show (he was heading there, too), and we got to chatting.

 

It turns out he’s the founder of Trinamic, a German company that designs chips for motion control. They have just started an SOI project with X-fab as the foundry. He’s very clear and enthusiastic about what he expects SOI to do for them. It’s for a high-volume app in small, precision motor control for things like video surveillance cameras.

 

This is an encouraging indication of just how far the SOI ecosystem is reaching! (We have an interview coming up with the folks at X-fab, btw, so keep an eye out for that.)

 

We’ll also have lots more from China, including interviews and profiles of the institutes and companies that are major players in the SOI ecosystem there. It’s truly an incredible place to be right now.

 

SiTime’s SOI-MEMS in MegaChips-Bosch Sensortec Solution for Realtime Health and Fitness Tracking in Smartphones & Wearables

SiTime’s SOI-MEMS solution is a key part of a new realtime health and fitness tracking solution from MegaChips called “frizz”. MegaChips has announced a partnership with Bosch Sensortec to provide a complete reference design for use of frizz in smartphones, wearables and other personal devices allowing consumers to monitor their activities in real time (read the press release here).

This marks SiTime’s first major announcement since becoming a subsidiary of Mega chips. SiTime leverages SOI-MEMS for high-performance, ultra-low power, ultra-slim timing solutions. (SiTime contributed an excellent piece to ASN a few years ago explaining their SOI edge – you can still read it here.)

SiTimeShignonB_image01Piyush Sevalia, SiTime marketing EVP, said, “SiTime’s groundbreaking MEMS and programmable analog technologies allow us to deliver game-changing MEMS timing solutions. Our MHz and kHz solutions provide the best accuracy, the smallest size and the lowest power, all of which are ideally suited for wearable electronics and internet of things (IoT).”

Frizz is a motion sensor hub with a 32bit DSP based motion engine that can realize high performance calculations used in processing algorithms with ultra-low power consumption in lieu of a microprocessor. MegaChips’ ultra-low power frizz, combined with the SiTime SiT1602 programmable MHz oscillator and Bosch Sensortec MEMS sensors provide more meaningful data, easy interpretation, higher accuracy and ultra-low power critical for longer battery life.

The joint frizz and Bosch Sensortec solution is available now from MegaChips (extensive information is available here).

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

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This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

TowerJazz — Interview With SVP Marco Racanelli: What’s Driving Strong SOI-Based Design Wins?

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

 

 

TowerJazzLogo_2014LR

 

 

 

 

ASN recently spoke with TowerJazz SVP Marco Racanelli about when the specialty foundry leverages SOI – and why.

Advanced Substrate News (ASN): Can you tell us briefly about TowerJazz’s overall vision and position in the market? 

Marco Racanelli (MR):  TowerJazz is the foundry leader for the manufacture of specialty semiconductor devices.  By “specialty” semiconductor devices, we mean those that require technology with some degree of specialization beyond commodity CMOS, for example in applications such as analog, RF, power, CMOS Image Sensor, and MEMS.  We invest in specialty process technology and manufacturing capacity around the world to fuel our growth (today we have manufacturing facilities in the US, Israel and Japan).

The TowerJazz fab in Newport Beach, CA.

The TowerJazz fab in Newport Beach, CA.

ASN: What kinds of chips does TowerJazz propose customers put on SOI? Why? 

MR: SOI on high resistivity substrates provides excellent RF isolation for customers working on front-end modules (FEMs) for wireless communication products.  Specifically for RF switches, thin device silicon layers result in low junction capacitance which is favorable for achieving high isolation.  We have had some customers leverage our SiGe BiCMOS technologies on SOI to integrate improved RF switching capabilities and achieve better isolation among circuit blocks.  Finally, some TowerJazz customers use thick film SOI for MEMS.  The silicon layer in SOI is used to fabricate beams for electro-mechanical structures and devices, e.g. MEMS resonators.

ASN: What are the growth drivers (end-markets, trends) for your SOI-based services? 

MR: Each generation of smart phones has required increasing numbers of RF ports to support multiple standards and functions e.g. 3G, 4G, 802.11, diversity antenna.  The need for longer handset battery life is driving implementation of RF-SOI based antenna tuner products to improve antenna efficiency.

 

Click to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

Click image to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

ASN: What are the advantages in moving to SOI-based technologies? 

MR: In some markets such as FEMs, the performance advantages of SOI are required to enable these RF products in CMOS; bulk technologies simply can’t provide the required isolation and low capacitance to meet the most demanding 4G/LTE specifications.  Thicker film SOI can support SiGe bipolar devices with significantly lower collector-to-substrate capacitance than their bulk counterparts.  In high voltage products, SOI dielectric isolation can simplify the design process, reduce latch-up risk, and allow a much more compact design than junction-isolated technologies.

Inside the TowerJazz Newport Beach Facility (Fab 3)

Inside the TowerJazz Newport Beach Facility (Fab 3)

ASN: Are there particular regions where you see especially high growth for SOI-based offerings? 

MR: We see broad adoption of SOI in all major phone platforms.  Our strongest growth and largest market for SOI is in the US although we see some Asia customers as well. The end customers are more evenly distributed between the US and Asia primarily.

ASN: Last year, you announced your RF-SOI had the industry’s best figure of merit for antenna switch and antenna tuning applications. What are you seeing there in terms of design wins? 

MR: We are seeing very strong design wins and production ramp of SOI in our factories.

 

American Semiconductor's  FleX-MCU™ product family leverages an SOI starting wafer.  (Courtesy: American Semiconductor)

American Semiconductor’s FleX-MCU™ product family leverages an SOI starting wafer.
(Courtesy: American Semiconductor)

ASN: American Semi partnered with TowerJazz on flexible ICs, which leverage SOI.  What sort of applications is that technology going into?  

MR: The potential for flexible ICs is very broad. For Aerospace and Defense, key areas of interest are ‘wearable’ circuits, introducing ICs and systems into soldiers’ field clothes and gear, creating a radar system that conforms to the entire body of an aircraft, sea vehicle, or any UAV or drone.  The ideas can be countless – the path is to reduce or eliminate the rigid form and fit of mobile electronics and integrate these electronics into a lighter weight, smaller and more flexible material.

ASN: Cavendish Kinetics announced that they’d be collaborating with you on RF-MEMS for mobile, which could be on SOI.  Is that available, and if so, can you tell us about it?

MR: We continue to work with Cavendish and have announced impressive reliability results with their devices; these are available through Cavendish directly.

ASN: Can you tell us more about the forthcoming 0.18 TS18SOI integrated power platform? 

MR: This platform is targeting a number of applications, the dominant one being in automotive and will include high-voltage devices, 0.18um CMOS for integration of digital and power management functions along with non-volatile-memory.  SOI in this case helps isolate the devices from the substrate allowing flexibility in applying voltages without turning on junctions that can lead to leakage or latch-up and in some cases helps reduce die-size by improving isolation allowing devices to be closer together.

ASN: Looking down the road, where/how do SOI-based technologies fit into your outlook for the future?  

MR: SOI particularly for RF is a significant focus for TowerJazz and we continue to invest in new technology and propagating the technology we have to multiple factories to increase capacity available to our customers.  While RF dominates our SOI consumption, we also see a good future for SOI in power management and MEMS and other sensor applications.

 

TGS2014_logo-LR

 

 

 

 

TowerJazz will be presenting its SOI and other processes at its upcoming Technical Global Symposiums (TGS) taking place in Europe (18 September 2014), the US (19 November 14) and Japan (10 December 2014). To find out more and register for TGS, please visit: http://www.towerjazz.com/tgs/

 

 

 

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Dr. Marco Racanelli has served as TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group since September 2008. Previously, he served as Vice President of Technology & Engineering, Aerospace & Defense General Manager for Jazz Semiconductor.

 Prior to Jazz, Dr. Racanelli held several positions at Conexant Systems and Rockwell Semiconductor since 1996 in the area of technology development where he helped establish industry leadership in SiGe and BiCMOS and MEMS technology, and built a strong design support organization. Prior to Rockwell, Dr. Racanelli worked at Motorola, Inc., where he contributed to bipolar, SiGe and SOI development for its Semiconductor Products Sector.

 Dr. Racanelli received a Ph.D. and a M.S. in Electrical and Computer Engineering from Carnegie Mellon University, and a B.Sc. in Electrical Engineering from Lehigh University. He holds over 35 U.S. patents.

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Interview: Leti CEO Malier on the FD-SOI Breakthrough; Leti Days in Grenoble (24-26 June) & Semicon West

Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM.  Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.

To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.

ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news.  (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).

LaurentMalierLeti

Laurent Malier, CEO of CEA-Leti

Here are some excerpts from our conversation.

Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?

Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost.  In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology

 

ASN: In which areas did Leti contribute to FD-SOI development?

LM:  Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention.  Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.

Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.

 

ASN: Do you see opportunities for FD-SOI in IoT?

LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data.  You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise.  Look for more announcements coming up at Leti Days.

LetiDays2014

Tronics Manufactures the First Piezoresistive Nanowire 6DOF Inertial MEMS (SOI)

Tronics_SOI_MEMS      Leti_NMEMS_Ultimes_V2

A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in the industry, and Tronics says further optimization will make it the smallest. Besides its size advantage, the piezoresistive nanowire based technology significantly decreases power consumption and allows manufacturing of all sensor types (accelerometers, gyroscopes, magnetometers, pressure sensor and microphone) using a common process flow.

This first functional batch is an important milestone towards high volume production. The industrialization work will continue through 2014, with the first commercial samples available in Q4 2014. An ASIC is also being designed and will be available in 2014 to complete the sensor platform. In addition to the 6DOF device, Tronics has also designed a very compact 9DOF monolithic MEMS. Samples will be available by the end of this year.

Target applications for this new generation of inertial devices are those where size and/or power are key: wearable devices, smartphones and tablets.

IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.

smart-stacking

So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

Soitec has licensed some of its intellectual property portfolio related to back-side illumination technology for image sensors to TSMC

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, has licensed some of its intellectual property (IP) portfolio related to back-side illumination (BSI) technology for image sensors to TSMC. BSI is a key enabling technology in the race to develop small-pixel, high-quality image sensors used in consumer products such as digital cameras, smart phones and other portable electronics.  In this case, the BSI technology uses some of the key process steps of Soitec’s Smart Stacking™ generic technology.

The company also announced that it has received ISO 22301:2012 certification for its Bernin site (near Grenoble, in South-East France). This international standard provides a framework for companies in implementing procedures that will ensure the continuity of their critical businesses during exceptional circumstances. Soitec, the first ISO 22301:2012 certified company in France, has thus received recognition for the quality of its business continuity management system to protect the company from disruptive incidents (fires, unavailability of its information system, pandemics, malicious acts, etc.) by reducing their potential impact on its business.

In solar news, Soitec announced its newest concentrated photovoltaic (CPV) module featuring a record power-generating efficiency of 31.8 percent. The new module, which is already in industrial volume production, has the highest efficiency of any commercial product available for multi-megawatt installations.

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).