April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.
Wow, were we precient.
Consider some of the topics we covered in that first edition, back in April of 2005:
FinFET on SOI (that was at 45nm)
NXP (then Philips) massive use of SOI for automotive chips (they were already running 3 million SOI-based transceivers a week back then)
a piece on low-power design with SOI by Jean-Luc Pelloie, who’s now an ARM Fellow and the company’s Director of SOI Technology
Intel had just published their first photonics on SOI papers in Nature (and yes, their photonics program is absolutely still on SOI)
ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.
The presentation is now posted on SlideShare (click here to see it).
It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.
If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.
We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)
Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.
Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.
And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.
In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.
So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.
The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.
I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.
In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.
With warm regards,
Semicon China (Shanghai, 17-21 March 2015) was an awe-inspiring event. The sheer size and the energy were dazzling. But it was the investment plans prompted by the government’s injection of RMB 120 billion (US$19.6 billion) last fall in seed money for the industry with supporting local funds pouring in that was clearly the source of a lot of adrenalin and M&A talk.
China’s industry is in high gear, still posting double-digit growth. But here’s the rub: while China consumes about half of the world’s roughly US$ $350 billion in chips (2015, WSTS), fabs in China only account for 2.5% of worldwide revenue. They’d like to see that change in a big way, and fast.
Hence Beijing’s IC Investment Fund, which is expected to continue to be expanded. SEMI estimates that the total government (central plus local) funds will reach US$100 billion, plus it’s prompting the creation and growth of additional local government and industry funds. (Dr. Adam He at SEMI has done an excellent job explaining Beijing’s investment strategy – you can see his summary here.) New VC funds are popping up everywhere, and existing ones are being augmented.
Which is why everybody was calling it the best time the industry’s ever seen. In his talk, Handel Jones of IBS, called it a once-in-a-lifetime opportunity.
This should represent significant opportunities for the SOI ecosystem in China. China foundries are offering RF-SOI already (click here to read about the Shanghai RF-SOI Workshop). And it is worth noting that China’s R&D institutes have deep expertise in all things SOI.
FD-SOI is an important topic (click here to see an ASN piece on FD-SOI by a professor at a top Beijing institute from last year, and here for more about the recent Shanghai FD-SOI workshop). China’s designers are hot on FD-SOI, too. (Did you hear about how the Beijing cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015? Read about it here.)
SOI-based MEMS, power, and sensors products are also already produced in China’s foundries. In fact SOI was a strategic focus by key institutes like SIMIT under the national “Innovation 2020” 5-year plan launched in 2010.
In terms of SOI wafers, China’s wafer leader, Simgui also works closely with Soitec, the world’s SOI wafer leader. Not surprisingly, theirs was a busy stand at Semicon China.
The Hot Topic: M&A
During the keynotes and industry sessions, M&A were central themes, as China looks beyond its borders for expertise. Hardly a talk went by that didn’t touch on this topic, all emphasizing that 1 + 1 > 2, and hammering home the importance of holding on to top talent in takeover scenarios. With each new slide, a sea of smartphones raised above the crowd to capture the onscreen tips.
In fact, with the IC Investment Fund taking center stage, the head of China Merger & Acquisition at Goldman Sachs gave the audience a primer on the M&A process. China, he noted, is now number two for M&A worldwide, just behind the US. While in the past the activity was “inbound”, China’s companies are now active on a transnational scale. This year will be an M&A record breaker for the semiconductor industry in China.
China’s expats are returning in droves from abroad, founding new companies. New industrial parks like the one out by the Shanghai airport are attracting major investors.
Big Show, Small World
This was the biggest Semicon ever, with 2750 booths covering 57,000m2 (over 600,000 sq. ft – more than three times the size of West) and over 50,000 visitors (almost twice what they got at West+Intersolar last year).
But Semicon China also had its small-world moments that show just how far SOI is reaching. Consider this. I was on the metro in Shanghai, heading over to Semicon, reading the show program. The guy next to me asked a question about the show (he was heading there, too), and we got to chatting.
It turns out he’s the founder of Trinamic, a German company that designs chips for motion control. They have just started an SOI project with X-fab as the foundry. He’s very clear and enthusiastic about what he expects SOI to do for them. It’s for a high-volume app in small, precision motor control for things like video surveillance cameras.
This is an encouraging indication of just how far the SOI ecosystem is reaching! (We have an interview coming up with the folks at X-fab, btw, so keep an eye out for that.)
We’ll also have lots more from China, including interviews and profiles of the institutes and companies that are major players in the SOI ecosystem there. It’s truly an incredible place to be right now.
SiTime’s SOI-MEMS solution is a key part of a new realtime health and fitness tracking solution from MegaChips called “frizz”. MegaChips has announced a partnership with Bosch Sensortec to provide a complete reference design for use of frizz in smartphones, wearables and other personal devices allowing consumers to monitor their activities in real time (read the press release here).
This marks SiTime’s first major announcement since becoming a subsidiary of Mega chips. SiTime leverages SOI-MEMS for high-performance, ultra-low power, ultra-slim timing solutions. (SiTime contributed an excellent piece to ASN a few years ago explaining their SOI edge – you can still read it here.)
Piyush Sevalia, SiTime marketing EVP, said, “SiTime’s groundbreaking MEMS and programmable analog technologies allow us to deliver game-changing MEMS timing solutions. Our MHz and kHz solutions provide the best accuracy, the smallest size and the lowest power, all of which are ideally suited for wearable electronics and internet of things (IoT).”
Frizz is a motion sensor hub with a 32bit DSP based motion engine that can realize high performance calculations used in processing algorithms with ultra-low power consumption in lieu of a microprocessor. MegaChips’ ultra-low power frizz, combined with the SiTime SiT1602 programmable MHz oscillator and Bosch Sensortec MEMS sensors provide more meaningful data, easy interpretation, higher accuracy and ultra-low power critical for longer battery life.
The joint frizz and Bosch Sensortec solution is available now from MegaChips (extensive information is available here).
Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM. Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.
To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.
ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).
Here are some excerpts from our conversation.
Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?
Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost. In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology
ASN: In which areas did Leti contribute to FD-SOI development?
LM: Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention. Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.
Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.
ASN: Do you see opportunities for FD-SOI in IoT?
LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data. You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise. Look for more announcements coming up at Leti Days.
A year after announcing the industrialization of CEA-Leti’s breakthrough M&NEMS technologies, Tronics has successfully designed and manufactured the first batch of six-degrees-of-freedom (6DOF) MEMS chips, with 3 accelerometers and 3 gyroscopes on a single die (press release here). Built on SOI wafers, with a die size of less than 4mm2, this 6DOF MEMS chip is one of the smallest in the industry, and Tronics says further optimization will make it the smallest. Besides its size advantage, the piezoresistive nanowire based technology significantly decreases power consumption and allows manufacturing of all sensor types (accelerometers, gyroscopes, magnetometers, pressure sensor and microphone) using a common process flow.
This first functional batch is an important milestone towards high volume production. The industrialization work will continue through 2014, with the first commercial samples available in Q4 2014. An ASIC is also being designed and will be available in 2014 to complete the sensor platform. In addition to the 6DOF device, Tronics has also designed a very compact 9DOF monolithic MEMS. Samples will be available by the end of this year.
Target applications for this new generation of inertial devices are those where size and/or power are key: wearable devices, smartphones and tablets.
If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.
Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI) in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.
Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.
In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents. This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.
So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.
For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.
In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.
One example of how effective our IP policy is came about in 1997 when we contracted with Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.
Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.
The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.
Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.
Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.
The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level. We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.
In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.
Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.
The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.
The complete list of posters and presentations can be seen in the technical program.
This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration. Check the list of participants on those links, and you will see that major players in the field are joining us!
Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.
There will be 2 short courses this year, and 2 fundamentals classes. Those educational tracks are available to you even if you do not register for the full conference.
On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..
Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).
On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.
You could also prefer to take the opportunity to visit the Monterey area.
The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest. The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.
To take full advantage of this outstanding event, register now!
Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.
The latest conference updates are available on the S3S website (http://S3Sconference.org).