Tag Archive silicon-on-insulator

ByGianni PRATA

Shanghai More-Than-Moore Presentations Now Posted on SOI Consortium Website

Presentations given at the ‘Beyond Computing’ Innovative Technologies Symposium (March 2015 in Shanghai) are now available on the SOI Consortium website (click here to see the list). The Symposium covered MEMS, semiconductor manufacturing, RF and power, which are key topics for the fast growing “More than Moore” industry. The one-day, closed-door symposium was organized by members of the SOI Consortium and the Shanghai Industrial μTechnology Research Institute (SITRI) to facilitate exchanges with industry leaders in China.

ByGianni PRATA

New Semico Study on SOI Apps, Opps & Markets

Research and consulting group Semico has issued a new report entitled SOI Update 2015: Finding New Applications (for information on getting a copy of the report, click here). As described on the Semico website: “With the recent growth in RF-SOI for switches and integrated solutions for RF functions such as power amplifiers and transceivers, the opportunities for growth in SOI wafer demand have once again garnered a lot of attention. In addition, as the industry transitions to very complex and expensive finFET technology, SOI is providing a high performance, low power option to semiconductor vendors who do not want take on the challenges of finFETs. This report explores the markets, products and outlook for SOI wafer adoption over the next five years.”

ByAdministrator

Huge Success of Semicon China: Opportunities in a Fast-Changing Landscape

SemiconBannerlores

Semicon China (Shanghai, 17-21 March 2015) was an awe-inspiring event.   The sheer size and the energy were dazzling. But it was the investment plans prompted by the government’s injection of RMB 120 billion (US$19.6 billion) last fall in seed money for the industry with supporting local funds pouring in that was clearly the source of a lot of adrenalin and M&A talk.

 

China’s industry is in high gear, still posting double-digit growth. But here’s the rub: while China consumes about half of the world’s roughly US$ $350 billion in chips (2015, WSTS), fabs in China only account for 2.5% of worldwide revenue. They’d like to see that change in a big way, and fast.

 

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

Hence Beijing’s IC Investment Fund, which is expected to continue to be expanded. SEMI estimates that the total government (central plus local) funds will reach US$100 billion, plus it’s prompting the creation and growth of additional local government and industry funds. (Dr. Adam He at SEMI has done an excellent job explaining Beijing’s investment strategy – you can see his summary here.) New VC funds are popping up everywhere, and existing ones are being augmented.

 

Which is why everybody was calling it the best time the industry’s ever seen. In his talk, Handel Jones of IBS, called it a once-in-a-lifetime opportunity.

 

This should represent significant opportunities for the SOI ecosystem in China. China foundries are offering RF-SOI already (click here to read about the Shanghai RF-SOI Workshop). And it is worth noting that China’s R&D institutes have deep expertise in all things SOI.

 

FD-SOI is an important topic (click here to see an ASN piece on FD-SOI by a professor at a top Beijing institute from last year, and here for more about the recent Shanghai FD-SOI workshop). China’s designers are hot on FD-SOI, too. (Did you hear about how the Beijing cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015? Read about it here.)

 

SOI-based MEMS, power, and sensors products are also already produced in China’s foundries. In fact SOI was a strategic focus by key institutes like SIMIT under the national “Innovation 2020” 5-year plan launched in 2010.

 

In terms of SOI wafers, China’s wafer leader, Simgui also works closely with Soitec, the world’s SOI wafer leader. Not surprisingly, theirs was a busy stand at Semicon China.

 

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

 

The Hot Topic: M&A

 

During the keynotes and industry sessions, M&A were central themes, as China looks beyond its borders for expertise. Hardly a talk went by that didn’t touch on this topic, all emphasizing that 1 + 1 > 2, and hammering home the importance of holding on to top talent in takeover scenarios. With each new slide, a sea of smartphones raised above the crowd to capture the onscreen tips.

 

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

 

In fact, with the IC Investment Fund taking center stage, the head of China Merger & Acquisition at Goldman Sachs gave the audience a primer on the M&A process. China, he noted, is now number two for M&A worldwide, just behind the US. While in the past the activity was “inbound”, China’s companies are now active on a transnational scale. This year will be an M&A record breaker for the semiconductor industry in China.

 

China’s expats are returning in droves from abroad, founding new companies. New industrial parks like the one out by the Shanghai airport are attracting major investors.

 

 

 

Big Show, Small World

 

This was the biggest Semicon ever, with 2750 booths covering 57,000m2 (over 600,000 sq. ft – more than three times the size of West) and over 50,000 visitors (almost twice what they got at West+Intersolar last year).

 

But Semicon China also had its small-world moments that show just how far SOI is reaching. Consider this. I was on the metro in Shanghai, heading over to Semicon, reading the show program. The guy next to me asked a question about the show (he was heading there, too), and we got to chatting.

 

It turns out he’s the founder of Trinamic, a German company that designs chips for motion control. They have just started an SOI project with X-fab as the foundry. He’s very clear and enthusiastic about what he expects SOI to do for them. It’s for a high-volume app in small, precision motor control for things like video surveillance cameras.

 

This is an encouraging indication of just how far the SOI ecosystem is reaching! (We have an interview coming up with the folks at X-fab, btw, so keep an eye out for that.)

 

We’ll also have lots more from China, including interviews and profiles of the institutes and companies that are major players in the SOI ecosystem there. It’s truly an incredible place to be right now.

 

ByAdministrator

RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more)

RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.

In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.

The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.

IBM

IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.

IBM_RFSOI_LTE

 

Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.

IBM_RFSOI_IoT

He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.

IBM_RFSOI_wafers_lowres

(You might also want to also refer to the IBM RF-SOI presentations given recently in Shanghai and Tokyo.)

ST

In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.

ST_RFSOI_roadmap

Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.

ST_RFSOI_PA

ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)

GlobalFoundries

In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.

GF_RFSOI_why

GF is the foundry partner for Peregrine (now part of Murata), and he showed how the GlobalONE PA integration is an excellent example of innovation opportunities.

GF_RFSOI_Peregrine

With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.

GF_RFSOI_FDSOI_filters

 

Incize

Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.

Imec

Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.

More Workshops Coming

If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

ByAdministrator

Big Boost for FD-SOI Momentum Seen at SF Workshop – Part 1 of 3: The FD-SOI Presentations (ST, Samsung, EDA & Design Houses)

The FD-SOI/RF-SOI Workshop in San Francisco last week was a huge success. Over 150 people from over 80 companies attended the all-day event. There were excellent presentations, animated Q&A sessions, and lots of networking going on over coffee, lunch and cocktails.  It generated excellent press (click here to see the EETimes feature) and lots of activity on LinkedIn and Twitter.

Everyone agreed it was an outstanding day, with all the presenters emphasizing the value, availability and ramp of FD-SOI. Feedback from the presenters indicates that the workshop spurred a significant boost in interest and opportunities.  As one participant noted, “This was very credible.”

If you didn’t make it to SF, we’ll cover the highlights in three ASN posts over the next few days (yes, it was that good!). Here in Part 1, we’ll cover the FD-SOI presentations. In Part 2, we’ll listen in on what was said during the panel discussion on FD-SOI. And in Part 3, we’ll take a look at the RF-SOI presentations. The actual presentations will all be posted shortly on the SOI Consortium website – keep checking back. But for now, here are some snapshots.

ST

ST’s CTO Philippe Magarshack presented on FD-SOI Advantages for Applications and Ecosystem. He was very clear on the value proposition of FD-SOI, with multiple examples (and a tip of the hat to Soitec, which enabled ST with industrial FD-SOI substrate).

ST’s now got 18 active FD-SOI projects underway, he said. What’s driving it?  FD-SOI is all about integration, he pointed out: digital, analog/mixed-signal and RF for starters. Beyond mobile, he cited three key application segments:

  • networking infrastructure apps – thanks to low SER (soft error rates)
  • IoT – especially for ultra-low voltage
  • automotive – with a good summary of the value (see slide) and an example from video analytics (see slide).

ST_FDSOI_automotive

 

ST_FDSOI_video

He also provided a summary of the key design advantages:

  • effective DVFS
  • FBB (forward body bias) for dynamic transistor Vt (threshold voltage) control
  • simple analog integration (a distinct advantage over bulk and FinFET)
  • best SER (soft error rate)

ST_FDSOIadv

With foundry partner Samsung and a complete design platform, the ecosystem is now in place, he concluded.

Samsung

Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI had a very clear message on the FD-SOI foundry offer: they are in business!

In his presentation, 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm, he covered the technology migration history: scaling, material then structure innovation.

Driving home the message that 28nm will be a long-lived node, he said the PDK’s ready, foundry services are ready and they’re taking orders. (In fact, there was a whole team from Samsung there, answering additional questions and following up with prospective customers during the breaks.)

Kelvin showed manufacturability and reliability data, and PPA (power, performance, area) benchmarks (see slide).

Samsung28FDSOIppa

For wearable apps, of course, low power is a must. Here, body biasing and low Vdd (supply voltage) are key, and again, 28nm FD-SOI shines (see slide).

Samsung28FDSOIvdd

EDA & IP

Next came excellent presentations by the EDA giants.

Mike McAweeney, Sr. Director IP Product Sales presented Synopsys FD-SOI IP Solutions.

Amir Bar-Niv, Senior Group Director, Product Management, Design IP at Cadence presented FD-SOI: Ecosystem and IP Design.

These were largely the same presentations given by these companies at the Tokyo FD-SOI workshop in December. Click here for ASN coverage of that event and details on those presentations.

Design Experience

Ben-Hamida, High Speed Analog Design Manager, Ciena presented the company’s view of the value of FD-SOI in their new 100Gb/s transceiver (see slide). He was very enthusiastic in his support of FD-SOI, and its ability to deliver on its promises.

Ciena_FDSOI

And finally, Shirley Jin, Sr. Director of Engineering at design house Verisilicon presented very compelling benchmarking data on an ARM Cortex A-7 in her presentation, 28nm FD-SOI Design/IP Infrastructure (see slide). Shirley gave a similar presentation in Tokyo in December. Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. Her presentation presented extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_FDSOI_ARMbenchmark2

 

Members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

And stay tuned for Part 2 of ASN’s SF Workshop coverage – where we’ll cover the panel discussion, and the big news that Cisco’s on board with an FD-SOI chip of their own. Part 3 will cover the RF-SOI presentations, and the massive rate of innovation seen there.

By

How SOI wafers for RF predict LTE-A/5G device performance

Soitec has developed an innovative metrology and metric for ensuring that devices built on our latest SOI wafers for RF will meet the draconian demands of LTE-Advanced (LTE-A) and 5G network standards.

For smartphones and tablets to handle LTE-A and 5G, they need RF devices with much higher linearity than those running over the current 2G, 3G, 4G and LTE network generations. These next generation network standards require mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

Soitec recently announced eSI90, our newest generation of trap-rich, high-resistivity SOI wafers for LTE-A and 5G. eSI90 extends our existing line of eSITM (enhanced Signal Integrity) wafers, the first generation of which are currently being used by leading manufactures to produce more than a billion RF devices every quarter.

This article gives an overview of how Soitec developed a new metric using innovative metrology on its wafers in order to predict the RF performance of final devices manufactured on eSI substrates. (Readers wanting greater detail can also consult our complete white paper on the subject, which is freely available to download here.)

Wafer specs evolve to meet new standards

To address the different communication standards and functions used in front-end modules, Soitec, the leader in SOI technology, has developed two flavors of RF-SOI products – high-resistivity (HR)-SOI and Enhanced Signal Integrity TM (eSI) SOI – both of which are compatible with standard CMOS processes. While standard HR-SOI wafers (which we introduced over a decade ago) are capable of meeting 2G or 3G requirements, eSI SOI can achieve much higher linearity and isolation specifications, allowing designers to address some of the most stringent LTE requirements. (We detailed how advanced RF design challenges are solved by eSI wafers in a 2013 ASN article – you can still read it here.) This paves the way for integrating more functions on a device with better RF performance at competitive cost.

eSI_SoitecUCLwafer

Soitec’s enhanced Signal Integrity™ (eSI) wafers integrate a trap-rich layer under the insulating BoX in a high-resistivity (HR) SOI wafer (Image courtesy of Soitec)

 

eSI wafers leverage the addition of a “trap-rich” layer to high-resistivity (HR) SOI wafers, an approach that was developed by UCL and Soitec (that project was covered in an ASN piece explaining the technical details at the time – you can read it here).

 

Change at all levels

The IIP3 linearity requirements for 3G are +65dBm. For LTE, they increased to +72dBm, and for LTE-A, they are over +90dBm. For RF designers, this has added substantially to the complexity of RF Front-End Modules (FEMs), and entails multiple changes for each of the main functions: switches, power amplifiers, power management and antenna tuners.

RFSOI_FEM_3G

Example of Front-End Module Block Diagram for 3G

RFSOI_FEM_LTE

Example of Front-End Module Block Diagram for LTE

 

These latest front-end modules need to support more bands, higher frequency bands from 700 MHz to 3.5 GHz, larger bands from 20 MHz to100 MHz and carrier aggregation downlink and uplink, sometimes on adjacent bands. This means:

  • A proliferation of switches on top of the antenna switch including diversity, power-mode and antenna-swapping switches
  • Advanced, tunable power-amplifier architectures to achieve compact and cost-effective multi-mode, multi-band transmission in a single broadband power amplifier
  • Advanced power management: with an envelope-tracking system approach, the efficiency of broadband power amplifiers will be close to or as good as that of single-band power amplifiers
  • Advanced wide-band antenna: with an antenna-tuner system performing either impedance matching and/or aperture tuning, an antenna can efficiently cover bands with frequencies from 700 MHz to 3.5 GHz with optimum efficiency and a smaller footprint

To meet the required performance, many changes are happening at all levels, from systems, architectures, design, manufacturing processes, devices – right down to where it all starts: the substrates. The substrates on which RF devices are manufactured have a significant impact on the level of performance that the final chips will be capable of achieving.

Characterizing eSI wafers

To quantify the performance designers can expect from an eSI SOI substrate, Soitec has now developed an innovative characterization method based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide. This solution is used today throughout the Soitec eSI product line to ensure the substrates will enable the expected RF performance in the finished devices.

We predict the RF harmonic distortion performance of the substrate immediately after the eSI SOI substrates are fabricated and before any devices are manufactured on them. This prediction is provided through a metric we call the harmonic quality factor (HQF).

HQF correlates with the second harmonic distortion generated from a 900-MHz signal applied to a coplanar waveguide (CPW) deposited on the substrate.

The CPWs are implemented on sample test wafers by depositing aluminum metal lines on the buried oxide of eSI SOI wafers after the Smart Cut process has been completed and the top silicium removed.

Then a 900-MHZ fundamental tone is applied on one end of the CPW line and the HD2 signal is measured at the other, providing a value of the HD2 generated by the substrate. Then, using the same wafers, a Spreading Resistance Profiling (SRP) technique measures the resistivity of the material at different depths under the buried oxide.

Next, we use a proprietary algorithm to compute the series of measures. The algorithm, tuned to match various HD2 values, takes into account the resistivity of the substrates weighted by the depth of the measure, and gives us the HQF.

Soitec has implemented this metrology on its production eSI SOI wafers and is sampling products to carry the HQF measurement.

To address different market requirements, we set our HQFmax specification at -80 dBm for eSI-G1 (first-generation eSI product) and at -90 dBm for our eSI90 (second-generation eSI product).

Soitec_RFSOI_eSI90_HQF

HQF specifications for Soitec’s 1st and 2nd generation eSI products (eSI-G1i and eSI90, respectively) correlated with linearity requirements.

Conclusion

HQF metrology, conducted at the substrate level, provides a reliable measure of the finished devices’ RF performance. It is now being used by Soitec to report the expected RF linearity performance of ICs manufactured with RF-SOI substrates.

As a solution addressing the current and next generation of RF standards, eSI SOI wafers are enabling this market by meeting some of the most difficult LTE and LTE Advanced linearity requirements. Soitec is able to provide its customers with the eSI SOI substrates that meet their desired level of RF performance.

ByAdministrator

Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too

The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide.  However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo.

In part 1 of ASN’s coverage of the workshop (click here if you missed it), we took a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis. Here in part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

Low Power SOC design with RF circuit by the FD-SOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Corporation

This presentation details Sony’s work on an 28nm FD-SOI version of its CXD5600GF Global Navigation Satellite System receiver LSI for smartphones and mobile products. When the bulk version was first released in 2013, the 10mW power consumption made it the industry’s lowest.  Now, with the 28nm FD-SOI version, they’ve gotten that down to a staggering 1mW – suitable for wearables. The presentation leads off by answering the question: Why FD-SOI? Sony engineers set themselves the challenge of a 0.6V target supply voltage for all logic, SRAM and analog (down from 1.1V in the previous generation). FD-SOI, especially leveraging body biasing, would enable them to attain this goal, providing a wide range of options for optimizing speed, power and area. The various steps and TEGs  (test element groups) are detailed in this presentation, and compared with 28nm and 40nm bulk. The advantages for low-power RF were particularly compelling.  This presentation has generated enormous attention in the press and in social media. For example, a week after EETimes published Sony Joins FD-SOI Club, it had been shared almost 200 times on LinkedIn.

Sony_Tokyo_FDSOI_GPS

(Courtesy: Sony)

 

Creation of high performance IP for FD-SOI by Kevin Yee, Director of Marketing, Cadence

As noted in this presentation, Cadence has existing solutions for 28nm FD-SOI, 14nm FD-SOI and 14nm FinFET-SOI. They have provided full design enablement for ST and Samsung processes. This presentation shows several examples of IP.

Cadence_Tokyo_FDSOI

(Courtesy: Cadence)

 

28nm FD-SOI Design/IP Infrastructure by Shirley Jin, Sr. Director of Engineering, VeriSilicon

Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. This presentation presents extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_Tokyo_28FDSOI_ARMbenchmark

Designing with FD-SOI – Benefits and Challenges by Huzefa Cutlerywala, Sr. Dir. Technical Solutions, Open-Silicon

Open-Silicon is a leader in traditional ASIC solutions, derivative and platform SoCs, hardware and software design and production handoffs. They are a channel partner for ST’s FD-SOI in Japan, have pipe-clean design flows for FD-SOI, and are currently taping out an FD-SOI test chip for a customer. They see FD-SOI as ideal for consumer and networking/telecom/storage/compute applications. This presention lists what they see as the benefits (which are impressive) and challenges (which are fairly minor), and provides some details on GPU and DSP cores.

OpenSilicon_Tokyo_FDSOI_DSPcore

(Courtesy: Open-Silicon)

 

Ultra Low Power Memory Solutions for FD-SOI by Paul Wells, CEO, SureCore

SureCore develops ultra-low power embedded SRAM IP. Making the point that memory typically dominates SoC area and can consume 70% of the power, SureCore sees FD-SOI as an elegant solution. Working samples of their SRAM solution in ST’s 28nm FD-SOI were received in March 2014, showing a 50% dynamic power savings, and high performance at low operating voltage. Extensive comparisons are given in this presentation.

Surecore_Tokyo_FDSOI_SRAM

(Courtesy: SureCore)

 

Synopsys FD-SOI IP Solutions by Mike McAweeney, Sr. Director, IP Product Sales, Synopsys

This presentation gives quite a detailed rundown of the ST-Synopsys 28FD-SOI IP program. Synopsys licenses a comprehensive, silicon-validated 28nm FD-SOI IP portfolio to Samsung’s foundry customers and other manufacturing partners. FD-SOI customers contract with Synopsys for standard Synopsys IP titles, with Synopsys customer support, part numbers, documentation and standard views. Slides 7 and 8 detail the commonly used interface, analog and display IPs available through Synopsys.

(Courtesy: Synopsys)

(Courtesy: Synopsys)

 

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

ByAdministrator

Tokyo FD-SOI/RF-SOI Workshop (part 1): Samsung, ST presentations & more

A dozen excellent presentations on FD-SOI and RF-SOI were made by industry leaders at the recent workshop in Tokyo. Here in part 1 of ASN’s coverage, we’ll take a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis.

In part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

28FD-SOI: cost effective low power solution for long lived 28nm node by Yongjoo Jeon, Principle Engineer in Foundry Marketing, Samsung

This presentation makes the point that cost and power are equally critical
 factors in the long life foreseen for the 28nm node. (Samsung, of course, is offering ST’s FD-SOI technology on a foundry basis.) In particular, this presentation shows how FD-SOI is especially well-suited for low-power
 IoT apps. (btw, Semiwiki just published an excellent analysis of this Samsung presentation – you can read it here.) The process was successfully qualified in September 2014.

SamsungFDSOI_lowVDD

(Courtesy: Samsung)

SamsungFDSOIprocesscost

(Courtesy: Samsung)

 

FD-SOI advantages for applications and ecosystem by Kirk Ouellette, Director Digital Product Group, STMicroelectronics

As FD-SOI both improves power efficiency and brings high flexibility to SoC integration, this presentation points up the target app benefits:

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

  • For Consumer products, it’s optimized SoC integration with mixed signal and RF; Energy efficiency under all thermal conditions; Optimized leakage in idle mode
  • For IoT, it’s low-cost, ultra-low voltage operation, high scalability and efficient RF and analog integration
  • For networking infrastructure, it’s energy-efficient multicores, effective DVFS and excellent memory performance
  • For automotive, it’s handling leakage at high-temps and high reliability (especially SER re: memory).

RF-SOI: Redefining mobility through the Front End Module by Masashi Arimoto, Technical Executive, Mobile Platform, IBM Microelectronics Japan

In 2006, IBM started transforming a 200mm fab into a specialty foundry. RF-SOI and SiGe were key technologies for cell phone and WiFi front end modules (FEM).  Mobile is key for driving the business of IBM: for infrastructure, for Cloud and for Big Data/analytics. Having shipped over 8 billion RF-SOI chips (>1300 tapeouts) to top mobile customers on its 7RF SOI technology, the company recently announced a new process: 7SW SOI, which packs 30% more performance into a 30% smaller space. They’re seeing ever stronger demand, which IoT will only increase. (Interesting to note that IBM also now sees 300mm FD-SOI as an opportunity for the heart and soul of the cell phone: the application processors.)

(Courtesy: IBM)

(Courtesy: IBM)

RF-SOI and FD-SOI Market Opportunities by Handel Jones, CEO, IBS

Industry guru Handel Jones (read his ASN pieces here) gets into the details of what IoT means in terms of chips, and where and when growth will be happening. Don’t miss his detailed slides on die and wafer cost for the various nodes of FD-SOI, bulk and FinFET (see slides 20-26) – FD-SOI comes out the clear winner in terms of cost benefits. He then explores the various RF segments.

 

ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration by Flavio Benetti, DPG Group VP – Networking Products Division GM, STMicroelectronics

(Courtesy: STMicroelectronics)

(Courtesy: STMicroelectronics)

Starting with a review of RF trends, this presenation shows how evolutions in the LTE wireless standard for this high-growth market are driving RF Front End Modules (FEM) to unprecedented complexity. ST sees RF-SOI integration as the right answer to that complexity (RF-SOI is of course already the leading technology in smartphone RF switches.) Slide 7 (see illustration) shows the explosive growth in the total annual market (TAM) for RF-SOI wafers. ST’s H9SOI_FEM offering pushes FEM integration to new heights, integrating switching, power amps, antenna tuning, energy management, LNA and filtering, all with best-in-class performance. This is an area in which ST is offering high-capacity foundry services, handling billions of units/year. (ST did an excellent ASN article detailing H9SOI_FEM last year – if you missed it, click here to read it now.)

 

Development of X-ray Sensor with SOI Pixel Technology by Masao Okihara, Device Technology Development Division, Manufacturing Headquarters, LAPIS Semiconductor

This presentation gives on update of the ongoing and fascinating work by a major consortium developing a one-chip monolithic X-ray sensor device on FD-SOI (this was also covered in ASN when the project was first getting underway – you can read that piece here. Oki, which is now Lapis, is providing the foundry services).

~ ~ ~

The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

ByAdministrator

LTE-A/5G: Bring it on. Next-gen Soitec eSI90 wafers predict & improve RF performance.

The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.

SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit.  That’s for 2G, 3G and now 4G and LTE.

But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.

Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.

SOIwafers_Soitec_lowres

SOI wafers. (Courtesy: Soitec)

But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.

Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).

The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).

So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.

Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.

To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.

The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.

When it comes to next-gen mobile design, innovation really does start at the substrate level.

ByGianni PRATA

Sony’s FD-SOI GPS makes EETimes headlines — and quite a buzz.

A new EETimes article entitled Sony Joins FD-SOI Club by Chief International Correspondent Junko Yoshida has created a tremendous buzz (click here to read it). The piece covers Sony’s presentation at the latest RF/FD-SOI workshop in Tokyo (many of the presentation are now posted here). Sony described their design experience with porting a GPS chip to 28nm FD-SOI, which resulted in a whopping 10x power reduction, down to just 1mW.  Already the world’s smallest, lowest-power chip, the move to FD-SOI gives it a huge edge in mobile IoT and wearables, where battery life is critical.  The response to the EETimes article was phenomenal. Within the first couple of days, it already had been shared over 90 times on LinkedIn and 50 on Facebook and Twitter.